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| author | Renlin Li <renlin.li@arm.com> | 2015-04-30 15:52:24 +0000 |
|---|---|---|
| committer | Renlin Li <renlin@gcc.gnu.org> | 2015-04-30 15:52:24 +0000 |
| commit | 9c004c58b3aba3c2ffa55ad31d35c8be0b6b5df4 (patch) | |
| tree | 2807c966466738b7b2ad1b459adf49963129c870 /gcc | |
| parent | e2165bd7d51059cb68a75f808f0ee31251268536 (diff) | |
| download | gcc-9c004c58b3aba3c2ffa55ad31d35c8be0b6b5df4.zip gcc-9c004c58b3aba3c2ffa55ad31d35c8be0b6b5df4.tar.gz gcc-9c004c58b3aba3c2ffa55ad31d35c8be0b6b5df4.tar.bz2 | |
[PATCH][AARCH64]Define vec_shr as an unspec, use shl for big-endian.
gcc/
2015-04-30 Renlin Li <renlin.li@arm.com>
* config/aarch64/aarch64-simd.md (vec_shr): Defined as an unspec.
* config/aarch64/iterators.md (unspec): Add UNSPEC_VEC_SHR.
gcc/testsuite/
2015-04-30 Renlin Li <renlin.li@arm.com>
Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/vect-reduc-or_1.c: New.
From-SVN: r222635
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 7 | ||||
| -rw-r--r-- | gcc/config/aarch64/iterators.md | 1 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/vect-reduc-or_1.c | 34 |
5 files changed, 48 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7fa0a11..40d71fc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2015-04-30 Renlin Li <renlin.li@arm.com> + + * config/aarch64/aarch64-simd.md (vec_shr): Defined as an unspec. + * config/aarch64/iterators.md (unspec): Add UNSPEC_VEC_SHR. + 2015-04-30 Jan Hubicka <hubicka@ucw.cz> PR ipa/65873 diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index b843744..5342c3d 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -783,12 +783,13 @@ ;; For 64-bit modes we use ushl/r, as this does not require a SIMD zero. (define_insn "vec_shr_<mode>" [(set (match_operand:VD 0 "register_operand" "=w") - (lshiftrt:VD (match_operand:VD 1 "register_operand" "w") - (match_operand:SI 2 "immediate_operand" "i")))] + (unspec:VD [(match_operand:VD 1 "register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_VEC_SHR))] "TARGET_SIMD" { if (BYTES_BIG_ENDIAN) - return "ushl %d0, %d1, %2"; + return "shl %d0, %d1, %2"; else return "ushr %d0, %d1, %2"; } diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 1fdff04..498358a 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -278,6 +278,7 @@ UNSPEC_PMULL ; Used in aarch64-simd.md. UNSPEC_PMULL2 ; Used in aarch64-simd.md. UNSPEC_REV_REGLIST ; Used in aarch64-simd.md. + UNSPEC_VEC_SHR ; Used in aarch64-simd.md. ]) ;; ------------------------------------------------------------------- diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3ab0afe..b669784 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2015-04-30 Renlin Li <renlin.li@arm.com> + + * gcc.target/aarch64/vect-reduc-or_1.c: New. + 2015-04-30 Marek Polacek <polacek@redhat.com> * c-c++-common/Wbool-compare-3.c: New test. diff --git a/gcc/testsuite/gcc.target/aarch64/vect-reduc-or_1.c b/gcc/testsuite/gcc.target/aarch64/vect-reduc-or_1.c new file mode 100644 index 0000000..c1d6b2f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-reduc-or_1.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all" } */ +/* Write a reduction loop to be reduced using whole vector right shift. */ + +extern void abort (void); + +unsigned char in[8] __attribute__((__aligned__(16))); + +int +main (unsigned char argc, char **argv) +{ + unsigned char i = 0; + unsigned char sum = 1; + + for (i = 0; i < 8; i++) + in[i] = (i + i + 1) & 0xfd; + + /* Prevent constant propagation of the entire loop below. */ + asm volatile ("" : : : "memory"); + + for (i = 0; i < 8; i++) + sum |= in[i]; + + if (sum != 13) + { + __builtin_printf ("Failed %d\n", sum); + abort (); + } + + return 0; +} + +/* { dg-final { scan-tree-dump "Reduce using vector shifts" "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ |