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| author | Tejas Belagod <tejas.belagod@arm.com> | 2013-11-22 15:31:57 +0000 |
|---|---|---|
| committer | Tejas Belagod <belagod@gcc.gnu.org> | 2013-11-22 15:31:57 +0000 |
| commit | 8fcc1c1fc2aaef9e008ed240739d9796185dac39 (patch) | |
| tree | 0d5e3f094d95e5916a34428d9de9ac07b98b0b16 /gcc | |
| parent | e58bf20adf7d275f6241f5e335c7342fecffb94c (diff) | |
| download | gcc-8fcc1c1fc2aaef9e008ed240739d9796185dac39.zip gcc-8fcc1c1fc2aaef9e008ed240739d9796185dac39.tar.gz gcc-8fcc1c1fc2aaef9e008ed240739d9796185dac39.tar.bz2 | |
aarch64-simd.md (vec_pack_trunc_<mode>, [...]): Swap source ops for big-endian.
2013-11-22 Tejas Belagod <tejas.belagod@arm.com>
gcc/
* config/aarch64/aarch64-simd.md (vec_pack_trunc_<mode>,
vec_pack_trunc_v2df, vec_pack_trunc_df): Swap source ops for big-endian.
From-SVN: r205268
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 27 |
2 files changed, 25 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 00ccbbc..958f61b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2013-11-22 Tejas Belagod <tejas.belagod@arm.com> + * config/aarch64/aarch64-simd.md (vec_pack_trunc_<mode>, + vec_pack_trunc_v2df, vec_pack_trunc_df): Swap source ops for big-endian. + +2013-11-22 Tejas Belagod <tejas.belagod@arm.com> + * config/aarch64/aarch64-simd.md (aarch64_simd_vec_set<mode>): Adjust for big-endian element order. (aarch64_simd_vec_setv2di): Likewise. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 2774ec2..bfd524c 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -916,9 +916,11 @@ "TARGET_SIMD" { rtx tempreg = gen_reg_rtx (<VDBL>mode); + int lo = BYTES_BIG_ENDIAN ? 2 : 1; + int hi = BYTES_BIG_ENDIAN ? 1 : 2; - emit_insn (gen_move_lo_quad_<Vdbl> (tempreg, operands[1])); - emit_insn (gen_move_hi_quad_<Vdbl> (tempreg, operands[2])); + emit_insn (gen_move_lo_quad_<Vdbl> (tempreg, operands[lo])); + emit_insn (gen_move_hi_quad_<Vdbl> (tempreg, operands[hi])); emit_insn (gen_aarch64_simd_vec_pack_trunc_<Vdbl> (operands[0], tempreg)); DONE; }) @@ -931,7 +933,12 @@ (truncate:<VNARROWQ> (match_operand:VQN 1 "register_operand" "w")) (truncate:<VNARROWQ> (match_operand:VQN 2 "register_operand" "w"))))] "TARGET_SIMD" - "xtn\\t%0.<Vntype>, %1.<Vtype>\;xtn2\\t%0.<V2ntype>, %2.<Vtype>" + { + if (BYTES_BIG_ENDIAN) + return "xtn\\t%0.<Vntype>, %2.<Vtype>\;xtn2\\t%0.<V2ntype>, %1.<Vtype>"; + else + return "xtn\\t%0.<Vntype>, %1.<Vtype>\;xtn2\\t%0.<V2ntype>, %2.<Vtype>"; + } [(set_attr "type" "multiple") (set_attr "length" "8")] ) @@ -1469,9 +1476,12 @@ "TARGET_SIMD" { rtx tmp = gen_reg_rtx (V2SFmode); - emit_insn (gen_aarch64_float_truncate_lo_v2sf (tmp, operands[1])); + int lo = BYTES_BIG_ENDIAN ? 2 : 1; + int hi = BYTES_BIG_ENDIAN ? 1 : 2; + + emit_insn (gen_aarch64_float_truncate_lo_v2sf (tmp, operands[lo])); emit_insn (gen_aarch64_float_truncate_hi_v4sf (operands[0], - tmp, operands[2])); + tmp, operands[hi])); DONE; } ) @@ -1487,8 +1497,11 @@ "TARGET_SIMD" { rtx tmp = gen_reg_rtx (V2SFmode); - emit_insn (gen_move_lo_quad_v2df (tmp, operands[1])); - emit_insn (gen_move_hi_quad_v2df (tmp, operands[2])); + int lo = BYTES_BIG_ENDIAN ? 2 : 1; + int hi = BYTES_BIG_ENDIAN ? 1 : 2; + + emit_insn (gen_move_lo_quad_v2df (tmp, operands[lo])); + emit_insn (gen_move_hi_quad_v2df (tmp, operands[hi])); emit_insn (gen_aarch64_float_truncate_lo_v2sf (operands[0], tmp)); DONE; } |