[arm] Fix BE index for single-var vector initialisers (PR91060)

If a vector constructor has a single nonconstant element,
neon_expand_vector_init loads the constant lanes and then inserts the
nonconstant value.  The problem was that it was doing the insertion
using the arm_neon.h neon_vset_lane<mode> patterns, which use
architectural lane numbering rather than GCC lane numbering.

2019-07-10  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	PR target/91060
	* config/arm/iterators.md (V2DI_ONLY): New mode iterator.
	* config/arm/neon.md (vec_set<mode>_internal): Add a '@' prefix.
	(vec_setv2di_internal): Reexpress as...
	(@vec_set<V2DI_ONLY:mode>_internal): ...this.
	* config/arm/arm.c (neon_expand_vector_init): Use gen_vec_set_internal
	rather than gen_neon_vset_lane<mode>.

From-SVN: r273365

4 files changed, 22 insertions, 40 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e7004e3..4c75120 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2019-07-10  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR target/91060
+	* config/arm/iterators.md (V2DI_ONLY): New mode iterator.
+	* config/arm/neon.md (vec_set<mode>_internal): Add a '@' prefix.
+	(vec_setv2di_internal): Reexpress as...
+	(@vec_set<V2DI_ONLY:mode>_internal): ...this.
+	* config/arm/arm.c (neon_expand_vector_init): Use gen_vec_set_internal
+	rather than gen_neon_vset_lane<mode>.
+
 2019-07-10  Vladimir Makarov  <vmakarov@redhat.com>
 
 	PR target/91102
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index f42a7b1..81286ca 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -12471,7 +12471,7 @@ neon_expand_vector_init (rtx target, rtx vals)
   if (n_var == 1)
     {
       rtx copy = copy_rtx (vals);
-      rtx index = GEN_INT (one_var);
+      rtx merge_mask = GEN_INT (1 << one_var);
 
       /* Load constant part of vector, substitute neighboring value for
 	 varying element.  */
@@ -12480,38 +12480,7 @@ neon_expand_vector_init (rtx target, rtx vals)
 
       /* Insert variable.  */
       x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, one_var));
-      switch (mode)
-	{
-	case E_V8QImode:
-	  emit_insn (gen_neon_vset_lanev8qi (target, x, target, index));
-	  break;
-	case E_V16QImode:
-	  emit_insn (gen_neon_vset_lanev16qi (target, x, target, index));
-	  break;
-	case E_V4HImode:
-	  emit_insn (gen_neon_vset_lanev4hi (target, x, target, index));
-	  break;
-	case E_V8HImode:
-	  emit_insn (gen_neon_vset_lanev8hi (target, x, target, index));
-	  break;
-	case E_V2SImode:
-	  emit_insn (gen_neon_vset_lanev2si (target, x, target, index));
-	  break;
-	case E_V4SImode:
-	  emit_insn (gen_neon_vset_lanev4si (target, x, target, index));
-	  break;
-	case E_V2SFmode:
-	  emit_insn (gen_neon_vset_lanev2sf (target, x, target, index));
-	  break;
-	case E_V4SFmode:
-	  emit_insn (gen_neon_vset_lanev4sf (target, x, target, index));
-	  break;
-	case E_V2DImode:
-	  emit_insn (gen_neon_vset_lanev2di (target, x, target, index));
-	  break;
-	default:
-	  gcc_unreachable ();
-	}
+      emit_insn (gen_vec_set_internal (mode, target, x, merge_mask, target));
       return;
     }
 
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index e03a720..eca1663 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -186,6 +186,9 @@
 ;; Modes with 8-bit elements.
 (define_mode_iterator VE [V8QI V16QI])
 
+;; V2DI only (for use with @ patterns).
+(define_mode_iterator V2DI_ONLY [V2DI])
+
 ;; Modes with 64-bit elements only.
 (define_mode_iterator V64 [DI V2DI])
 
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 4bfe770..6333e0e 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -319,7 +319,7 @@
   "vld1.<V_sz_elem>\t{%q0}, %A1"
   [(set_attr "type" "neon_load1_1reg<q>")])
 
-(define_insn "vec_set<mode>_internal"
+(define_insn "@vec_set<mode>_internal"
   [(set (match_operand:VD_LANE 0 "s_register_operand" "=w,w")
         (vec_merge:VD_LANE
           (vec_duplicate:VD_LANE
@@ -340,7 +340,7 @@
 }
   [(set_attr "type" "neon_load1_all_lanes<q>,neon_from_gp<q>")])
 
-(define_insn "vec_set<mode>_internal"
+(define_insn "@vec_set<mode>_internal"
   [(set (match_operand:VQ2 0 "s_register_operand" "=w,w")
         (vec_merge:VQ2
           (vec_duplicate:VQ2
@@ -369,12 +369,12 @@
   [(set_attr "type" "neon_load1_all_lanes<q>,neon_from_gp<q>")]
 )
 
-(define_insn "vec_setv2di_internal"
-  [(set (match_operand:V2DI 0 "s_register_operand" "=w,w")
-        (vec_merge:V2DI
-          (vec_duplicate:V2DI
+(define_insn "@vec_set<mode>_internal"
+  [(set (match_operand:V2DI_ONLY 0 "s_register_operand" "=w,w")
+        (vec_merge:V2DI_ONLY
+          (vec_duplicate:V2DI_ONLY
             (match_operand:DI 1 "nonimmediate_operand" "Um,r"))
-          (match_operand:V2DI 3 "s_register_operand" "0,0")
+          (match_operand:V2DI_ONLY 3 "s_register_operand" "0,0")
           (match_operand:SI 2 "immediate_operand" "i,i")))]
   "TARGET_NEON"
 {