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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2014-04-08 17:50:45 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2014-04-08 17:50:45 +0000 |
| commit | 8418cf337f9eefbec5cfd722ddb1792314fe2daf (patch) | |
| tree | b4a0a354890bd69f8fa7ff8a45bf52a0fa06c58a /gcc | |
| parent | 6525783a221d88ef4e89a8e9dd01c7bfd82ec711 (diff) | |
| download | gcc-8418cf337f9eefbec5cfd722ddb1792314fe2daf.zip gcc-8418cf337f9eefbec5cfd722ddb1792314fe2daf.tar.gz gcc-8418cf337f9eefbec5cfd722ddb1792314fe2daf.tar.bz2 | |
re PR rtl-optimization/60763 (ICE in extract_insn starting with rev 208984)
gcc/
PR target/60763
* config/rs6000/vsx.md (vsx_xscvdpspn_scalar): Change input to DImode.
* config/rs6000/rs6000.md (reload_vsx_from_gprsf): Update accordingly.
Use gen_rtx_REG rather than simplify_gen_subreg for op0_di.
From-SVN: r209223
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 7 | ||||
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 2 |
3 files changed, 13 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f17809b..eb382a7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2014-04-08 Richard Sandiford <rdsandiford@googlemail.com> + + PR target/60763 + * config/rs6000/vsx.md (vsx_xscvdpspn_scalar): Change input to DImode. + * config/rs6000/rs6000.md (reload_vsx_from_gprsf): Update accordingly. + Use gen_rtx_REG rather than simplify_gen_subreg for op0_di. + 2014-04-08 Richard Biener <rguenther@suse.de> PR middle-end/60706 diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9e1df98..738011c 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -10029,13 +10029,16 @@ rtx op0 = operands[0]; rtx op1 = operands[1]; rtx op2 = operands[2]; - rtx op0_di = simplify_gen_subreg (DImode, op0, SFmode, 0); + /* Also use the destination register to hold the unconverted DImode value. + This is conceptually a separate value from OP0, so we use gen_rtx_REG + rather than simplify_gen_subreg. */ + rtx op0_di = gen_rtx_REG (DImode, REGNO (op0)); rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0); /* Move SF value to upper 32-bits for xscvspdpn. */ emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32))); emit_move_insn (op0_di, op2); - emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0)); + emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0_di)); DONE; } [(set_attr "length" "8") diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index a06cdd5..d83cdc3 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1223,7 +1223,7 @@ ;; Used by direct move to move a SFmode value from GPR to VSX register (define_insn "vsx_xscvspdpn_directmove" [(set (match_operand:SF 0 "vsx_register_operand" "=wa") - (unspec:SF [(match_operand:SF 1 "vsx_register_operand" "wa")] + (unspec:SF [(match_operand:DI 1 "vsx_register_operand" "wa")] UNSPEC_VSX_CVSPDPN))] "TARGET_XSCVSPDPN" "xscvspdpn %x0,%x1" |