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| author | Richard Stallman <rms@gnu.org> | 1993-06-26 20:50:27 +0000 |
|---|---|---|
| committer | Richard Stallman <rms@gnu.org> | 1993-06-26 20:50:27 +0000 |
| commit | 73ebbfdff0d75988af114269be5afe76f6709ab8 (patch) | |
| tree | ebe4b5e564aa860daccb4de2322ceab625d0927c /gcc | |
| parent | cd1db1088e0d55527415056906f5fab878253b0f (diff) | |
| download | gcc-73ebbfdff0d75988af114269be5afe76f6709ab8.zip gcc-73ebbfdff0d75988af114269be5afe76f6709ab8.tar.gz gcc-73ebbfdff0d75988af114269be5afe76f6709ab8.tar.bz2 | |
(movdf recognizer): Remove `&' from constraint for loading mem to cpu reg.
From-SVN: r4760
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/sparc/sparc.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 813ce84..d4b1660 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -1197,7 +1197,7 @@ }") (define_insn "" - [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand" "=T,U,f,r,Q,Q,f,&r") + [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand" "=T,U,f,r,Q,Q,f,r") (match_operand:DF 1 "reg_or_nonsymb_mem_operand" "U,T,f,r,f,r,Q,Q"))] "TARGET_FPU && (register_operand (operands[0], DFmode) |