driver-i386.c (host_detect_local_cpu): Add support for skylake.

gcc/

	* config/i386/driver-i386.c (host_detect_local_cpu): Add support
	for skylake.
	* config/i386/i386.c (PTA_SKYLAKE): New macros.
	(processor_alias_table): Add skylake description.
	(enum processor_model): Add skylake processor.
	(arch_names_table): Add skylake record.
	* doc/invoke.texi: Add skylake item.

gcc/testsuite/

	* gcc.target/i386/builtin_target.c: Add skylake check.

libgcc/

	* config/i386/cpuinfo.c (enum processor_subtypes): Add skylake.
	(get_intel_cpu): Likewise.

From-SVN: r226884

6 files changed, 37 insertions, 1 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bdaebcc..e404e66 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2015-08-14  Yuri Rumyantsev  <ysrumyan@gmail.com>
+
+	* config/i386/driver-i386.c (host_detect_local_cpu): Add support
+	for skylake.
+	* config/i386/i386.c (PTA_SKYLAKE): New macros.
+	(processor_alias_table): Add skylake description.
+	(enum processor_model): Add skylake processor.
+	(arch_names_table): Add skylake record.
+	* doc/invoke.texi: Add skylake item.
+
 2015-08-13  Andrew MacLeod  <amacleod@redhat.com>
 
 	* ira-int.h: Include recog.h.
diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index bc5239e..ec4cbec 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -755,6 +755,11 @@ const char *host_detect_local_cpu (int argc, const char **argv)
 	  /* Broadwell.  */
 	  cpu = "broadwell";
 	  break;
+	case 0x4e:
+	case 0x5e:
+	  /* Skylake.  */
+	  cpu = "skylake";
+	  break;
 	case 0x57:
 	  /* Knights Landing.  */
 	  cpu = "knl";
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index caec218..4a0986c 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -3285,6 +3285,8 @@ ix86_option_override_internal (bool main_args_p,
    | PTA_FMA | PTA_MOVBE | PTA_HLE)
 #define PTA_BROADWELL \
   (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
+#define PTA_SKYLAKE \
+  (PTA_BROADWELL | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES)
 #define PTA_KNL \
   (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
 #define PTA_BONNELL \
@@ -3347,6 +3349,7 @@ ix86_option_override_internal (bool main_args_p,
       {"haswell", PROCESSOR_HASWELL, CPU_NEHALEM, PTA_HASWELL},
       {"core-avx2", PROCESSOR_HASWELL, CPU_NEHALEM, PTA_HASWELL},
       {"broadwell", PROCESSOR_HASWELL, CPU_NEHALEM, PTA_BROADWELL},
+      {"skylake", PROCESSOR_HASWELL, CPU_NEHALEM, PTA_SKYLAKE},
       {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
       {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
       {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
@@ -35636,7 +35639,8 @@ fold_builtin_cpu (tree fndecl, tree *args)
     M_AMDFAM15H_BDVER4,
     M_INTEL_COREI7_IVYBRIDGE,
     M_INTEL_COREI7_HASWELL,
-    M_INTEL_COREI7_BROADWELL
+    M_INTEL_COREI7_BROADWELL,
+    M_INTEL_COREI7_SKYLAKE
   };
 
   static struct _arch_names_table
@@ -35658,6 +35662,7 @@ fold_builtin_cpu (tree fndecl, tree *args)
       {"ivybridge", M_INTEL_COREI7_IVYBRIDGE},
       {"haswell", M_INTEL_COREI7_HASWELL},
       {"broadwell", M_INTEL_COREI7_BROADWELL},
+      {"skylake", M_INTEL_COREI7_SKYLAKE},
       {"bonnell", M_INTEL_BONNELL},
       {"silvermont", M_INTEL_SILVERMONT},
       {"knl", M_INTEL_KNL},
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 0ae2e26..2871337 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -22404,6 +22404,12 @@ Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
 BMI, BMI2, F16C, RDSEED, ADCX and PREFETCHW instruction set support.
 
+@item skylake
+Intel Skylake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
+BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC and
+XSAVES instruction set support.
+
 @item bonnell
 Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
 instruction set support.
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2929fe4..36fc67e 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2015-08-14  Yuri Rumyantsev  <ysrumyan@gmail.com>
+
+	* gcc.target/i386/builtin_target.c: Add skylake check.
+
 2015-08-13  Jeff Law  <law@redhat.com>
 
 	* gcc.dg/pr66314.c: Moved from here to ..
diff --git a/gcc/testsuite/gcc.target/i386/builtin_target.c b/gcc/testsuite/gcc.target/i386/builtin_target.c
index 068db23..300d208 100644
--- a/gcc/testsuite/gcc.target/i386/builtin_target.c
+++ b/gcc/testsuite/gcc.target/i386/builtin_target.c
@@ -85,6 +85,12 @@ check_intel_cpu_model (unsigned int family, unsigned int model,
 	      assert (__builtin_cpu_is ("corei7"));
 	      assert (__builtin_cpu_is ("broadwell"));
 	      break;
+	    case 0x4e:
+	    case 0x5e:
+	      /* Skylake.  */
+	      assert (__builtin_cpu_is ("corei7"));
+	      assert (__builtin_cpu_is ("skylake"));
+	      break;
 	    case 0x17:
 	    case 0x1d:
 	      /* Penryn.  */