diff options
| author | H.J. Lu <hongjiu.lu@intel.com> | 2017-08-07 11:47:22 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2017-08-07 04:47:22 -0700 |
| commit | 356512c0660a1f549c48128ab63cc56077d05db2 (patch) | |
| tree | 43c3854469f87c2a612ec2a2039830532e291265 /gcc | |
| parent | c8f34527b1c941f81e41df66e5d7cc2aedb453df (diff) | |
| download | gcc-356512c0660a1f549c48128ab63cc56077d05db2.zip gcc-356512c0660a1f549c48128ab63cc56077d05db2.tar.gz gcc-356512c0660a1f549c48128ab63cc56077d05db2.tar.bz2 | |
i386: Set priority to P_AES for Westmere
The difference between Nehalem and Westmere is AES. We should set
priority to P_AES for Westmere, not P_PROC_SSE4_2 which is for Nehalem.
Otherwise, we will pick Nehalem implementation on Westmere. Tested on
Westmere.
PR target/81743
* config/i386/i386.c (get_builtin_code_for_version): Set priority
to P_AES for Westmere.
From-SVN: r250915
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 17 |
2 files changed, 17 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 440f6da..a78b1a7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-08-07 H.J. Lu <hongjiu.lu@intel.com> + + PR target/81743 + * config/i386/i386.c (get_builtin_code_for_version): Set priority + to P_AES for Westmere. + 2017-08-07 Jonathan Yong <10walls@gmail.com> * config/i386/mingw.opt (fset-stack-executable): Removed. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index a598465..c0b6015 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -33417,13 +33417,18 @@ get_builtin_code_for_version (tree decl, tree *predicate_list) break; case PROCESSOR_NEHALEM: if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AES) - arg_str = "westmere"; + { + arg_str = "westmere"; + priority = P_AES; + } else - /* We translate "arch=corei7" and "arch=nehalem" to - "corei7" so that it will be mapped to M_INTEL_COREI7 - as cpu type to cover all M_INTEL_COREI7_XXXs. */ - arg_str = "corei7"; - priority = P_PROC_SSE4_2; + { + /* We translate "arch=corei7" and "arch=nehalem" to + "corei7" so that it will be mapped to M_INTEL_COREI7 + as cpu type to cover all M_INTEL_COREI7_XXXs. */ + arg_str = "corei7"; + priority = P_PROC_SSE4_2; + } break; case PROCESSOR_SANDYBRIDGE: if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_F16C) |