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| author | Michael Meissner <meissner@gcc.gnu.org> | 1995-04-25 19:46:08 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 1995-04-25 19:46:08 +0000 |
| commit | 17ea663341d6a003a9557966687297a3fe7987f6 (patch) | |
| tree | a388a2de15383ecdd28c1257f8173337f70adf11 /gcc | |
| parent | 2ac5334923c9b33370283b9ed6c1c70872d1ef7d (diff) | |
| download | gcc-17ea663341d6a003a9557966687297a3fe7987f6.zip gcc-17ea663341d6a003a9557966687297a3fe7987f6.tar.gz gcc-17ea663341d6a003a9557966687297a3fe7987f6.tar.bz2 | |
Do not allow DFs to use 2 register addressing if -msoft-float
From-SVN: r9441
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/rs6000/rs6000.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index fa196b2..0d3df3c 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1438,6 +1438,7 @@ struct rs6000_args {int words, fregno, nargs_prototype; }; } \ else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ && GET_CODE (XEXP (X, 1)) != CONST_INT \ + && (TARGET_HARD_FLOAT || (MODE) != DFmode) \ && (MODE) != DImode && (MODE) != TImode) \ { \ (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \ |