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| author | Andrew Pinski <apinski@cavium.com> | 2011-12-09 03:56:36 +0000 |
|---|---|---|
| committer | Andrew Pinski <pinskia@gcc.gnu.org> | 2011-12-08 19:56:36 -0800 |
| commit | 14f2a7e2b1a8c5c21603c095a848c895af5b7a10 (patch) | |
| tree | e1c0463ca3f8de98aaa5a7e786cc5710377208ff /gcc | |
| parent | fbf7be801c91a75bfae7b43cd169620743ba1f52 (diff) | |
| download | gcc-14f2a7e2b1a8c5c21603c095a848c895af5b7a10.zip gcc-14f2a7e2b1a8c5c21603c095a848c895af5b7a10.tar.gz gcc-14f2a7e2b1a8c5c21603c095a848c895af5b7a10.tar.bz2 | |
mips-cpus.def (octeon+): New CPU.
2011-12-08 Andrew Pinski <apinski@cavium.com>
* config/mips/mips-cpus.def (octeon+): New CPU.
* config/mips/mips-tables.opt: Regenerate.
* config/mips/mips.h (MIPS_CPP_SET_PROCESSOR): Emit '+' as 'P'.
2011-12-08 Andrew Pinski <apinski@cavium.com>
* cc.target/mips/mult-1.c: Forbid all Octeon processors.
* gcc.target/mips/dmult-1.c: Likewise.
* gcc.target/mips/branch-1.c: Likewise.
* gcc.target/mips/extend-1.c: Likewise.
From-SVN: r182152
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/mips/mips-cpus.def | 1 | ||||
| -rw-r--r-- | gcc/config/mips/mips-tables.opt | 3 | ||||
| -rw-r--r-- | gcc/config/mips/mips.h | 5 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/mips/branch-1.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/mips/dmult-1.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/mips/extend-1.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/mips/mult-1.c | 2 |
9 files changed, 25 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e6e29e5..43027e0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2011-12-08 Andrew Pinski <apinski@cavium.com> + + * config/mips/mips-cpus.def (octeon+): New CPU. + * config/mips/mips-tables.opt: Regenerate. + * config/mips/mips.h (MIPS_CPP_SET_PROCESSOR): Emit '+' as 'P'. + 2011-12-08 Bill Schmidt <wschmidt@linux.vnet.ibm.com> PR middle-end/39976 diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index 35fd516..39f46ab 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -145,3 +145,4 @@ MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY) /* MIPS64 Release 2 processors. */ MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY) +MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY) diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index 4e410f0..bd88526 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -603,3 +603,6 @@ Enum(mips_arch_opt_value) String(loongson3a) Value(79) Canonical EnumValue Enum(mips_arch_opt_value) String(octeon) Value(80) Canonical +EnumValue +Enum(mips_arch_opt_value) String(octeon+) Value(81) Canonical + diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 236afbb..ee40cfa 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -329,7 +329,10 @@ struct mips_cpu_info { \ macro = concat ((PREFIX), "_", (INFO)->name, NULL); \ for (p = macro; *p != 0; p++) \ - *p = TOUPPER (*p); \ + if (*p == '+') \ + *p = 'P'; \ + else \ + *p = TOUPPER (*p); \ \ builtin_define (macro); \ builtin_define_with_value ((PREFIX), (INFO)->name, 1); \ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9d4f286..8ad5ffe 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2011-12-08 Andrew Pinski <apinski@cavium.com> + + * cc.target/mips/mult-1.c: Forbid all Octeon processors. + * gcc.target/mips/dmult-1.c: Likewise. + * gcc.target/mips/branch-1.c: Likewise. + * gcc.target/mips/extend-1.c: Likewise. + 2011-12-08 Jason Merrill <jason@redhat.com> PR c++/51318 diff --git a/gcc/testsuite/gcc.target/mips/branch-1.c b/gcc/testsuite/gcc.target/mips/branch-1.c index 62d6bbb..2f4510f 100644 --- a/gcc/testsuite/gcc.target/mips/branch-1.c +++ b/gcc/testsuite/gcc.target/mips/branch-1.c @@ -2,7 +2,7 @@ but we test for "bbit" elsewhere. On other targets, we should implement the "if" statements using an "andi" instruction followed by a branch on zero. */ -/* { dg-options "-O2 forbid_cpu=octeon" } */ +/* { dg-options "-O2 forbid_cpu=octeon.*" } */ void bar (void); NOMIPS16 void f1 (int x) { if (x & 4) bar (); } diff --git a/gcc/testsuite/gcc.target/mips/dmult-1.c b/gcc/testsuite/gcc.target/mips/dmult-1.c index 517e43e..f8c0b8b 100644 --- a/gcc/testsuite/gcc.target/mips/dmult-1.c +++ b/gcc/testsuite/gcc.target/mips/dmult-1.c @@ -1,4 +1,4 @@ -/* { dg-options "forbid_cpu=octeon -mgp64" } */ +/* { dg-options "forbid_cpu=octeon.* -mgp64" } */ /* { dg-final { scan-assembler "\tdmult\t" } } */ /* { dg-final { scan-assembler "\tmflo\t" } } */ /* { dg-final { scan-assembler-not "\tdmul\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/extend-1.c b/gcc/testsuite/gcc.target/mips/extend-1.c index 4295106..5e93890 100644 --- a/gcc/testsuite/gcc.target/mips/extend-1.c +++ b/gcc/testsuite/gcc.target/mips/extend-1.c @@ -1,4 +1,4 @@ -/* { dg-options "-O -mgp64 forbid_cpu=octeon" } */ +/* { dg-options "-O -mgp64 forbid_cpu=octeon.*" } */ /* { dg-final { scan-assembler-times "\tdsll\t" 5 } } */ /* { dg-final { scan-assembler-times "\tdsra\t" 5 } } */ /* { dg-final { scan-assembler-not "\tsll\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/mult-1.c b/gcc/testsuite/gcc.target/mips/mult-1.c index 43dd08c..96961b0 100644 --- a/gcc/testsuite/gcc.target/mips/mult-1.c +++ b/gcc/testsuite/gcc.target/mips/mult-1.c @@ -1,6 +1,6 @@ /* For SI->DI widening multiplication we should use DINS to combine the two halves. For Octeon use DMUL with explicit widening. */ -/* { dg-options "-O -mgp64 isa_rev>=2 forbid_cpu=octeon" } */ +/* { dg-options "-O -mgp64 isa_rev>=2 forbid_cpu=octeon.*" } */ /* { dg-final { scan-assembler "\tdins\t" } } */ /* { dg-final { scan-assembler-not "\tdsll\t" } } */ /* { dg-final { scan-assembler-not "\tdsrl\t" } } */ |