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| author | Segher Boessenkool <segher@kernel.crashing.org> | 2019-07-01 23:58:47 +0200 |
|---|---|---|
| committer | Segher Boessenkool <segher@gcc.gnu.org> | 2019-07-01 23:58:47 +0200 |
| commit | a01d6debebd86b0cdf77be5dc1130fdf0a856a1d (patch) | |
| tree | ffdc12ca53312f46884d5e29d0d56a7f0796128d /gcc | |
| parent | 5cc8cb04de4285bfa85c16073e99185b41c38f85 (diff) | |
| download | gcc-a01d6debebd86b0cdf77be5dc1130fdf0a856a1d.zip gcc-a01d6debebd86b0cdf77be5dc1130fdf0a856a1d.tar.gz gcc-a01d6debebd86b0cdf77be5dc1130fdf0a856a1d.tar.bz2 | |
rs6000.md (signbit<mode>2_dm): Make this a parameterized name.
@signbit<mode>2_dm
* config/rs6000/rs6000.md (signbit<mode>2_dm): Make this a
parameterized name.
(signbit<mode>2): Use that name. Simplify.
From-SVN: r272912
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 10 |
2 files changed, 8 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index dad3442..00885e6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2019-07-01 Segher Boessenkool <segher@kernel.crashing.org> + + * config/rs6000/rs6000.md (signbit<mode>2_dm): Make this a + parameterized name. + (signbit<mode>2): Use that name. Simplify. + 2019-07-01 Joern Rennecke <joern.rennecke@riscy-ip.com> PR middle-end/66726 diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9ab9ceb..9e81df9 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -4857,13 +4857,7 @@ rtx tmp = gen_reg_rtx (DImode); rtx dest_di = gen_lowpart (DImode, dest); - if (<MODE>mode == KFmode) - emit_insn (gen_signbitkf2_dm (tmp, src)); - else if (<MODE>mode == TFmode) - emit_insn (gen_signbittf2_dm (tmp, src)); - else - gcc_unreachable (); - + emit_insn (gen_signbit2_dm (<MODE>mode, tmp, src)); emit_insn (gen_lshrdi3 (dest_di, tmp, GEN_INT (63))); DONE; } @@ -4893,7 +4887,7 @@ ;; After register allocation, if the _Float128 had originally been in GPRs, the ;; split allows the post reload phases to eliminate the move, and do the shift ;; directly with the register that contains the signbit. -(define_insn_and_split "signbit<mode>2_dm" +(define_insn_and_split "@signbit<mode>2_dm" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (unspec:DI [(match_operand:SIGNBIT 1 "gpc_reg_operand" "wa,r")] UNSPEC_SIGNBIT))] |