aarch64: Add ISA requirements to some SVE/SME md comments

The SVE and SME md files are divided into sections, with each
section often starting with a comment that lists the associated
mnemonics.  These lists usually include the base architecture
requirement in parentheses, if the base requirement is greater
than the baseline for the file.  This patch tries to be more
consistent about when we do that for the recently added SVE2p1
and SME2p1 extensions.

gcc/
	* config/aarch64/aarch64-sme.md: In the section comments, add the
	architecture requirements alongside some mnemonics.
	* config/aarch64/aarch64-sve2.md: Likewise.

2 files changed, 121 insertions, 113 deletions

diff --git a/gcc/config/aarch64/aarch64-sme.md b/gcc/config/aarch64/aarch64-sme.md
index 0f362671..e456218 100644
--- a/gcc/config/aarch64/aarch64-sme.md
+++ b/gcc/config/aarch64/aarch64-sme.md
@@ -533,7 +533,7 @@
 ;; ---- Table loads
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - LDR
+;; - LDR (SME2)
 ;; -------------------------------------------------------------------------
 
 (define_c_enum "unspec" [
@@ -635,7 +635,7 @@
 ;; ---- Table stores
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - STR
+;; - STR (SME2)
 ;; -------------------------------------------------------------------------
 
 (define_insn "aarch64_sme_str_zt0"
@@ -651,7 +651,7 @@
 ;; -------------------------------------------------------------------------
 ;; Includes:
 ;; - MOVA
-;; - MOVAZ
+;; - MOVAZ (SME2p1)
 ;; -------------------------------------------------------------------------
 
 (define_insn "@aarch64_sme_<optab><v_int_container><mode>"
@@ -813,7 +813,7 @@
 ;; -------------------------------------------------------------------------
 ;; Includes:
 ;; - MOVA
-;; - MOVAZ
+;; - MOVAZ (SME2p1)
 ;; -------------------------------------------------------------------------
 
 (define_insn "@aarch64_sme_<optab><mode><mode>"
@@ -1140,12 +1140,12 @@
 ;; ---- Binary arithmetic on ZA slice
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - ADD
-;; - BFADD
-;; - BFSUB
-;; - FADD
-;; - FSUB
-;; - SUB
+;; - ADD (SME2)
+;; - BFADD (SME_B16B16)
+;; - BFSUB (SME_B16B16)
+;; - FADD (SME2)
+;; - FSUB (SME2)
+;; - SUB (SME2)
 ;; -------------------------------------------------------------------------
 
 (define_insn "@aarch64_sme_<optab><mode>"
@@ -1202,8 +1202,8 @@
 ;; ---- Binary arithmetic, writing to ZA slice
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - ADD
-;; - SUB
+;; - ADD (SME2)
+;; - SUB (SME2)
 ;; -------------------------------------------------------------------------
 
 (define_insn "@aarch64_sme_<optab><mode>"
@@ -1270,10 +1270,10 @@
 ;; ---- [INT] Dot product
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - SDOT
-;; - SUDOT
-;; - UDOT
-;; - USDOT
+;; - SDOT (SME2)
+;; - SUDOT (SME2)
+;; - UDOT (SME2)
+;; - USDOT (SME2)
 ;; -------------------------------------------------------------------------
 
 (define_insn "@aarch64_sme_<optab><SME_ZA_SDI:mode><SME_ZA_BHIx24:mode>"
@@ -1411,10 +1411,10 @@
 ;; ---- [INT] Ternary widening arithmetic on ZA slice
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - SMLA
-;; - SMLS
-;; - UMLA
-;; - UMLS
+;; - SMLA (SME2)
+;; - SMLS (SME2)
+;; - UMLA (SME2)
+;; - UMLS (SME2)
 ;; -------------------------------------------------------------------------
 
 (define_insn "@aarch64_sme_<optab><VNx4SI_ONLY:mode><SVE_FULL_BHI:mode>"
@@ -1676,8 +1676,8 @@
 ;; -------------------------------------------------------------------------
 ;; ---- [INT] Sum of outer products
 ;; -------------------------------------------------------------------------
-;; - BMOPA
-;; - BMOPS
+;; - BMOPA (SME2)
+;; - BMOPS (SME2)
 ;; - SMOPA
 ;; - SMOPS
 ;; - SUMOPA
@@ -1752,8 +1752,8 @@
 ;; ---- [FP] Dot product
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - BFDOT
-;; - FDOT
+;; - BFDOT (SME2)
+;; - FDOT (SME2)
 ;; -------------------------------------------------------------------------
 
 (define_insn "@aarch64_sme_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx24:mode>"
@@ -1849,10 +1849,10 @@
 ;; ---- [FP] Ternary arithmetic on ZA slice
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - BFMLA
-;; - BFMLS
-;; - FMLA
-;; - FMLS
+;; - BFMLA (SME_B16B16)
+;; - BFMLS (SME_B16B16)
+;; - FMLA (SME2)
+;; - FMLS (SME2)
 ;; -------------------------------------------------------------------------
 
 (define_insn "@aarch64_sme_<optab><mode><mode>"
@@ -1948,10 +1948,10 @@
 ;; ---- [FP] Ternary widening arithmetic on ZA slice
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - BFMLAL
-;; - BFMLSL
-;; - FMLAL
-;; - FMLSL
+;; - BFMLAL (SME2)
+;; - BFMLSL (SME2)
+;; - FMLAL (SME2)
+;; - FMLSL (SME2)
 ;; -------------------------------------------------------------------------
 
 (define_insn "@aarch64_sme_<optab><VNx4SI_ONLY:mode><SVE_FULL_HF:mode>"
@@ -2086,8 +2086,8 @@
 ;; ---- [FP] Sum of outer products
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - BFMOPA
-;; - BFMOPS
+;; - BFMOPA (SME_B16B16)
+;; - BFMOPS (SME_B16B16)
 ;; - FMOPA
 ;; - FMOPS
 ;; -------------------------------------------------------------------------
@@ -2130,8 +2130,8 @@
 ;; ---- Table lookup
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - LUTI2
-;; - LUTI4
+;; - LUTI2 (SME2)
+;; - LUTI4 (SME2)
 ;; -------------------------------------------------------------------------
 
 (define_c_enum "unspec" [
diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md
index 219e9fc..d26c0c5 100644
--- a/gcc/config/aarch64/aarch64-sve2.md
+++ b/gcc/config/aarch64/aarch64-sve2.md
@@ -142,7 +142,7 @@
 ;; ---- Predicate to vector moves
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - PMOV (to vector)
+;; - PMOV (to vector) (SVE2p1)
 ;; -------------------------------------------------------------------------
 
 (define_insn "@aarch64_pmov_to_<mode>"
@@ -169,7 +169,7 @@
 ;; ---- Vector to predicate moves
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - PMOV (from vector)
+;; - PMOV (from vector) (SVE2p1)
 ;; -------------------------------------------------------------------------
 
 (define_insn "@aarch64_pmov_from_<mode>"
@@ -199,8 +199,8 @@
 ;; ---- 128-bit extending loads
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - LD1W (to .Q)
-;; - LD1D (to .Q)
+;; - LD1W (to .Q) (SVE2p1)
+;; - LD1D (to .Q) (SVE2p1)
 ;; -------------------------------------------------------------------------
 
 ;; There isn't really a natural way of representing these instructions
@@ -233,9 +233,9 @@
 ;; ---- 128-bit structure loads
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - LD2Q
-;; - LD3Q
-;; - LD4Q
+;; - LD2Q (SVE2p1)
+;; - LD3Q (SVE2p1)
+;; - LD4Q (SVE2p1)
 ;; -------------------------------------------------------------------------
 
 ;; Predicated LD[234]Q.
@@ -330,7 +330,7 @@
 ;; ---- 128-bit gather loads
 ;; -------------------------------------------------------------------------
 ;; Includes gather forms of:
-;; - LD1Q
+;; - LD1Q (SVE2p1)
 ;; -------------------------------------------------------------------------
 
 ;; Model this as operating on the largest valid element size, which is DI.
@@ -417,8 +417,8 @@
 ;; ---- 128-bit truncating stores
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - ST1W (from .Q)
-;; - ST1D (from .Q)
+;; - ST1W (from .Q) (SVE2p1)
+;; - ST1D (from .Q) (SVE2p1)
 ;; -------------------------------------------------------------------------
 
 ;; See the comment above the corresponding loads for a discussion about the
@@ -438,9 +438,9 @@
 ;; ---- 128-bit structure stores
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - ST2Q
-;; - ST3Q
-;; - ST4Q
+;; - ST2Q (SVE2p1)
+;; - ST3Q (SVE2p1)
+;; - ST4Q (SVE2p1)
 ;; -------------------------------------------------------------------------
 
 ;; Predicated ST[234].
@@ -515,7 +515,7 @@
 ;; ---- 128-bit scatter stores
 ;; -------------------------------------------------------------------------
 ;; Includes scatter form of:
-;; - ST1Q
+;; - ST1Q (SVE2p1)
 ;; -------------------------------------------------------------------------
 
 (define_insn "aarch64_scatter_st1q"
@@ -1326,12 +1326,12 @@
 ;; ---- [FP] Non-widening bfloat16 arithmetic
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - BFADD
-;; - BFMAX
-;; - BFMAXNM
-;; - BFMIN
-;; - BFMINNM
-;; - BFMUL
+;; - BFADD (SVE_B16B16)
+;; - BFMAX (SVE_B16B16)
+;; - BFMAXNM (SVE_B16B16)
+;; - BFMIN (SVE_B16B16)
+;; - BFMINNM (SVE_B16B16)
+;; - BFMUL (SVE_B16B16)
 ;; -------------------------------------------------------------------------
 
 ;; Predicated B16B16 binary operations.
@@ -1999,18 +1999,18 @@
 ;; ---- [FP] Mfloat8 Multiply-and-accumulate operations
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - FMLALB (vectors, FP8 to FP16)
-;; - FMLALT (vectors, FP8 to FP16)
-;; - FMLALB (indexed, FP8 to FP16)
-;; - FMLALT (indexed, FP8 to FP16)
-;; - FMLALLBB (vectors)
-;; - FMLALLBB (indexed)
-;; - FMLALLBT (vectors)
-;; - FMLALLBT (indexed)
-;; - FMLALLTB (vectors)
-;; - FMLALLTB (indexed)
-;; - FMLALLTT (vectors)
-;; - FMLALLTT (indexed)
+;; - FMLALB (vectors, FP8 to FP16) (FP8FMA)
+;; - FMLALT (vectors, FP8 to FP16) (FP8FMA)
+;; - FMLALB (indexed, FP8 to FP16) (FP8FMA)
+;; - FMLALT (indexed, FP8 to FP16) (FP8FMA)
+;; - FMLALLBB (vectors) (FP8FMA)
+;; - FMLALLBB (indexed) (FP8FMA)
+;; - FMLALLBT (vectors) (FP8FMA)
+;; - FMLALLBT (indexed) (FP8FMA)
+;; - FMLALLTB (vectors) (FP8FMA)
+;; - FMLALLTB (indexed) (FP8FMA)
+;; - FMLALLTT (vectors) (FP8FMA)
+;; - FMLALLTT (indexed) (FP8FMA)
 ;; -------------------------------------------------------------------------
 
 (define_insn "@aarch64_sve_add_<sve2_fp8_fma_op_vnx8hf><mode>"
@@ -2079,10 +2079,10 @@
 ;; ---- [FP] Mfloat8 dot products
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - FDOT (4-way, vectors)
-;; - FDOT (4-way, indexed)
-;; - FDOT (2-way, vectors)
-;; - FDOT (2-way, indexed)
+;; - FDOT (4-way, vectors) (FP8DOT4)
+;; - FDOT (4-way, indexed) (FP8DOT4)
+;; - FDOT (2-way, vectors) (FP8DOT2)
+;; - FDOT (2-way, indexed) (FP8DOT2)
 ;; -------------------------------------------------------------------------
 (define_insn "@aarch64_sve_dot<mode>"
   [(set (match_operand:SVE_FULL_HSF 0 "register_operand")
@@ -2576,10 +2576,10 @@
 ;; ---- [INT] Multi-vector narrowing unary arithmetic
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - SQCVT
-;; - SQCVTN
-;; - UQCVT
-;; - UQCVTN
+;; - SQCVT (SME2)
+;; - SQCVTN (SME2)
+;; - UQCVT (SME2)
+;; - UQCVTN (SME2)
 ;; -------------------------------------------------------------------------
 
 (define_insn "@aarch64_sve_<optab><VNx16QI_ONLY:mode><VNx16SI_ONLY:mode>"
@@ -2711,12 +2711,12 @@
 ;; ---- [INT] Multi-vector narrowing right shifts
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - SQRSHR
-;; - SQRSHRN
-;; - SQRSHRU
-;; - SQRSHRUN
-;; - UQRSHR
-;; - UQRSHRN
+;; - SQRSHR (SME2)
+;; - SQRSHRN (SVE2p1, SME2)
+;; - SQRSHRU (SME2)
+;; - SQRSHRUN (SVE2p1, SME2)
+;; - UQRSHR (SME2)
+;; - UQRSHRN (SVE2p1, SME2)
 ;; -------------------------------------------------------------------------
 
 (define_insn "@aarch64_sve_<sve_int_op><mode>"
@@ -3058,14 +3058,14 @@
 ;; ---- [FP<-FP] Widening conversions
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - BF1CVT
-;; - BF1CVTLT
-;; - BF2CVT
-;; - BF2CVTLT
-;; - F1CVT
-;; - F1CVTLT
-;; - F2CVT
-;; - F2CVTLT
+;; - BF1CVT (FP8)
+;; - BF1CVTLT (FP8)
+;; - BF2CVT (FP8)
+;; - BF2CVTLT (FP8)
+;; - F1CVT (FP8)
+;; - F1CVTLT (FP8)
+;; - F2CVT (FP8)
+;; - F2CVTLT (FP8)
 ;; - FCVTLT
 ;; -------------------------------------------------------------------------
 
@@ -3261,8 +3261,8 @@
 ;; ---- [FP<-FP] Multi-vector widening conversions
 ;; -------------------------------------------------------------------------
 ;; Includes the multi-register forms of:
-;; - FCVT
-;; - FCVTL
+;; - FCVT (SME_F16F16)
+;; - FCVTL (SME_F16F16)
 ;; -------------------------------------------------------------------------
 
 (define_insn "extendvnx8hfvnx8sf2"
@@ -3286,12 +3286,12 @@
 ;; ---- [FP<-FP] Multi-vector narrowing conversions
 ;; -------------------------------------------------------------------------
 ;; Includes the multi-register forms of:
-;; - BFCVT
-;; - BFCVTN
-;; - FCVT
-;; - FCVTN
-;; - FCVTNB
-;; - FCVTNT
+;; - BFCVT (SME2)
+;; - BFCVTN (SME2)
+;; - FCVT (SME2)
+;; - FCVTN (SME2)
+;; - FCVTNB (FP8)
+;; - FCVTNT (FP8)
 ;; -------------------------------------------------------------------------
 
 (define_insn "truncvnx8sf<mode>2"
@@ -3345,6 +3345,10 @@
 ;; -------------------------------------------------------------------------
 ;; ---- [FP<-INT] Multi-vector conversions
 ;; -------------------------------------------------------------------------
+;; Includes the multi-register forms of:
+;; - SCVTF (SME2)
+;; - UCVTF (SME2)
+;; -------------------------------------------------------------------------
 
 (define_insn "<optab><v_int_equiv><mode>2"
   [(set (match_operand:SVE_SFx24 0 "aligned_register_operand" "=Uw<vector_count>")
@@ -3357,6 +3361,10 @@
 ;; -------------------------------------------------------------------------
 ;; ---- [INT<-FP] Multi-vector conversions
 ;; -------------------------------------------------------------------------
+;; Includes the multi-register forms of:
+;; - FCVTZS (SME2)
+;; - FCVTZU (SME2)
+;; -------------------------------------------------------------------------
 
 (define_insn "<optab><mode><v_int_equiv>2"
   [(set (match_operand:<V_INT_EQUIV> 0 "aligned_register_operand" "=Uw<vector_count>")
@@ -3629,14 +3637,14 @@
 ;; ---- [INT] Reduction to 128-bit vector
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - ADDQV
-;; - ANDQV
-;; - EORQV
-;; - ORQV
-;; - SMAXQV
-;; - SMINQV
-;; - UMAXQV
-;; - UMINQV
+;; - ADDQV (SVE2p1)
+;; - ANDQV (SVE2p1)
+;; - EORQV (SVE2p1)
+;; - ORQV (SVE2p1)
+;; - SMAXQV (SVE2p1)
+;; - SMINQV (SVE2p1)
+;; - UMAXQV (SVE2p1)
+;; - UMINQV (SVE2p1)
 ;; -------------------------------------------------------------------------
 
 (define_insn "@aarch64_pred_reduc_<optab>_<mode>"
@@ -3653,11 +3661,11 @@
 ;; ---- [FP] Reduction to 128-bit vector
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - FADDQV
-;; - FMAXNMQV
-;; - FMAXQV
-;; - FMINNMQV
-;; - FMINQV
+;; - FADDQV (SVE2p1)
+;; - FMAXNMQV (SVE2p1)
+;; - FMAXQV (SVE2p1)
+;; - FMINNMQV (SVE2p1)
+;; - FMINQV (SVE2p1)
 ;; -------------------------------------------------------------------------
 
 (define_insn "@aarch64_pred_reduc_<optab>_<mode>"
@@ -3716,8 +3724,8 @@
 ;; ---- [INT,FP] HVLA permutes
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - DUPQ
-;; - EXTQ
+;; - DUPQ (SVE2p1)
+;; - EXTQ (SVE2p1)
 ;; -------------------------------------------------------------------------
 
 (define_insn "@aarch64_sve_dupq<mode>"