diff options
| author | Andrew Carlotti <andrew.carlotti@arm.com> | 2024-12-18 15:59:24 +0000 |
|---|---|---|
| committer | Andrew Carlotti <andrew.carlotti@arm.com> | 2025-01-10 14:12:12 +0000 |
| commit | 016e2f00d40d76676f38fb9d268ac550e5ec878a (patch) | |
| tree | 8f94e6fbfd4e845d84be26b47f4ed2334d9428df /gcc | |
| parent | e7f98d9603808b1c17106d3d9f2000bc34f2c50c (diff) | |
| download | gcc-016e2f00d40d76676f38fb9d268ac550e5ec878a.zip gcc-016e2f00d40d76676f38fb9d268ac550e5ec878a.tar.gz gcc-016e2f00d40d76676f38fb9d268ac550e5ec878a.tar.bz2 | |
docs: Document new hardreg PRE pass
gcc/ChangeLog:
* doc/passes.texi: Document hardreg PRE pass.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/doc/passes.texi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/gcc/doc/passes.texi b/gcc/doc/passes.texi index 59a1432..282fc1a 100644 --- a/gcc/doc/passes.texi +++ b/gcc/doc/passes.texi @@ -959,6 +959,12 @@ global constant and copy propagation. The source file for this pass is @file{gcse.cc}, and the LCM routines are in @file{lcm.cc}. +A third version of this pass is run on some targets to optimise assignments to +specific hard registers. This can be used in cases where a register has a +single purpose, such as specifying a mode as an extra input for specific +instructions (@pxref{mode switching optimization} for another way of handling +instruction modes). + @item Loop optimization This pass performs several loop related optimizations. @@ -1018,6 +1024,7 @@ combination approaches as well. The pass runs twice, once before register allocation and once after register allocation. The code is located in @file{late-combine.cc}. +@anchor{mode switching optimization} @item Mode switching optimization This pass looks for instructions that require the processor to be in a |