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| author | Jim Wilson <jimw@sifive.com> | 2018-09-26 21:06:01 +0000 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 2018-09-26 14:06:01 -0700 |
| commit | 01414d53cf3c062ca821de9ae48ba4c3db7d8ad7 (patch) | |
| tree | 3b673a581949377bb289082ef0a4ffbe325ff363 /gcc | |
| parent | d89fde46d7368b070e9cde3ca6a88f67b5643af9 (diff) | |
| download | gcc-01414d53cf3c062ca821de9ae48ba4c3db7d8ad7.zip gcc-01414d53cf3c062ca821de9ae48ba4c3db7d8ad7.tar.gz gcc-01414d53cf3c062ca821de9ae48ba4c3db7d8ad7.tar.bz2 | |
RISC-V: Add missing negate patterns.
gcc/
* config/riscv/riscv.md (subsi3_extended2): Add J constraint.
(negdi2, negsi2, negsi2_extended, negsi2_extended2): New.
From-SVN: r264655
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.md | 41 |
2 files changed, 43 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 69c754d..b13aaa8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2018-09-26 Jim Wilson <jimw@sifive.com> + + * config/riscv/riscv.md (subsi3_extended2): Add J constraint. + (negdi2, negsi2, negsi2_extended, negsi2_extended2): New. + 2018-09-26 Martin Sebor <msebor@redhat.com> * tree.c (zerop): Change return type to bool. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 95fbb28..4162dc5 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -514,16 +514,51 @@ (set_attr "mode" "SI")]) (define_insn "*subsi3_extended2" - [(set (match_operand:DI 0 "register_operand" "=r") + [(set (match_operand:DI 0 "register_operand" "= r") (sign_extend:DI - (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" " r") - (match_operand:DI 2 "register_operand" " r")) + (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" " rJ") + (match_operand:DI 2 "register_operand" " r")) 0)))] "TARGET_64BIT" "subw\t%0,%z1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) +(define_insn "negdi2" + [(set (match_operand:DI 0 "register_operand" "=r") + (neg:DI (match_operand:DI 1 "register_operand" " r")))] + "TARGET_64BIT" + "neg\t%0,%1" + [(set_attr "type" "arith") + (set_attr "mode" "DI")]) + +(define_insn "negsi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (neg:SI (match_operand:SI 1 "register_operand" " r")))] + "" + { return TARGET_64BIT ? "negw\t%0,%1" : "neg\t%0,%1"; } + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + +(define_insn "*negsi2_extended" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (neg:SI (match_operand:SI 1 "register_operand" " r"))))] + "TARGET_64BIT" + "negw\t%0,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + +(define_insn "*negsi2_extended2" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (subreg:SI (neg:DI (match_operand:DI 1 "register_operand" " r")) + 0)))] + "TARGET_64BIT" + "negw\t%0,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + ;; ;; .................... ;; |