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| author | GCC Administrator <gccadmin@gcc.gnu.org> | 2022-06-15 00:19:12 +0000 |
|---|---|---|
| committer | GCC Administrator <gccadmin@gcc.gnu.org> | 2022-06-15 00:19:12 +0000 |
| commit | e11091012fed75eb1148699a7a5662e5f72a57f0 (patch) | |
| tree | 2b37e7009910422bb6dd48e9a4bf20f48d6696c1 /gcc | |
| parent | d10b3b5c1f61c05b3cf1229d0bd961db3f8ee653 (diff) | |
| download | gcc-e11091012fed75eb1148699a7a5662e5f72a57f0.zip gcc-e11091012fed75eb1148699a7a5662e5f72a57f0.tar.gz gcc-e11091012fed75eb1148699a7a5662e5f72a57f0.tar.bz2 | |
Daily bump.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 20 | ||||
| -rw-r--r-- | gcc/DATESTAMP | 2 |
2 files changed, 21 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index afdc7be..6eb98d2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,23 @@ +2022-06-14 H.J. Lu <hjl.tools@gmail.com> + + Backported from master: + 2022-06-13 H.J. Lu <hjl.tools@gmail.com> + + * common/config/i386/cpuinfo.h (get_available_features): Require + AVX for F16C and VAES. + +2022-06-14 Philipp Tomsich <philipp.tomsich@vrull.eu> + + Backported from master: + 2022-06-02 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/riscv.cc (riscv_build_integer_1): Rewrite value as + (-1 << 31) for the single-bit case, when operating on (1 << 31) + in SImode. + * config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): Allow for + any single-bit value, moving the special case for (1 << 31) to + riscv_build_integer_1 (in riscv.c). + 2022-06-08 Max Filippov <jcmvbkbc@gmail.com> Backported from master: diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index f6e8eb7..fa673f3 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20220614 +20220615 |