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| author | Andrew Stubbs <ams@codesourcery.com> | 2020-03-26 21:22:45 +0000 |
|---|---|---|
| committer | Andrew Stubbs <ams@codesourcery.com> | 2022-10-12 11:41:11 +0100 |
| commit | b6c9e5f31954ae6a2b4a7ff1da04e8d3b585d4dc (patch) | |
| tree | d2daf64f6533be93b22654d1c98280c572f47c0b /gcc | |
| parent | 0915a9406904244697e1c9fbf7babb52eeb0d699 (diff) | |
| download | gcc-b6c9e5f31954ae6a2b4a7ff1da04e8d3b585d4dc.zip gcc-b6c9e5f31954ae6a2b4a7ff1da04e8d3b585d4dc.tar.gz gcc-b6c9e5f31954ae6a2b4a7ff1da04e8d3b585d4dc.tar.bz2 | |
amdgcn: Resolve insn conditions at compile time
GET_MODE_NUNITS isn't a compile time constant, so we end up with many
impossible insns in the machine description. Adding MODE_VF allows the insns
to be eliminated completely.
gcc/ChangeLog:
* config/gcn/gcn-valu.md
(<cvt_name><VCVT_MODE:mode><VCVT_FMODE:mode>2<exec>): Use MODE_VF.
(<cvt_name><VCVT_FMODE:mode><VCVT_IMODE:mode>2<exec>): Likewise.
* config/gcn/gcn.h (MODE_VF): New macro.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog.omp | 10 | ||||
| -rw-r--r-- | gcc/config/gcn/gcn-valu.md | 10 | ||||
| -rw-r--r-- | gcc/config/gcn/gcn.h | 24 |
3 files changed, 40 insertions, 4 deletions
diff --git a/gcc/ChangeLog.omp b/gcc/ChangeLog.omp index 087ac318..24dff91 100644 --- a/gcc/ChangeLog.omp +++ b/gcc/ChangeLog.omp @@ -3,6 +3,16 @@ Backport from mainline: 2022-10-11 Andrew Stubbs <ams@codesourcery.com> + * config/gcn/gcn-valu.md + (<cvt_name><VCVT_MODE:mode><VCVT_FMODE:mode>2<exec>): Use MODE_VF. + (<cvt_name><VCVT_FMODE:mode><VCVT_IMODE:mode>2<exec>): Likewise. + * config/gcn/gcn.h (MODE_VF): New macro. + +2022-10-12 Andrew Stubbs <ams@codesourcery.com> + + Backport from mainline: + 2022-10-11 Andrew Stubbs <ams@codesourcery.com> + * config/gcn/gcn-modes.def (VECTOR_MODE): Add new modes V32QI, V32HI, V32SI, V32DI, V32TI, V32HF, V32SF, V32DF, V16QI, V16HI, V16SI, V16DI, V16TI, V16HF, V16SF, V16DF, diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index c932bc3..cecaa1c 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -2884,8 +2884,9 @@ [(set (match_operand:VCVT_FMODE 0 "register_operand" "= v") (cvt_op:VCVT_FMODE (match_operand:VCVT_MODE 1 "gcn_alu_operand" "vSvB")))] - "gcn_valid_cvt_p (<VCVT_MODE:MODE>mode, <VCVT_FMODE:MODE>mode, - <cvt_name>_cvt)" + "MODE_VF (<VCVT_MODE:MODE>mode) == MODE_VF (<VCVT_FMODE:MODE>mode) + && gcn_valid_cvt_p (<VCVT_MODE:MODE>mode, <VCVT_FMODE:MODE>mode, + <cvt_name>_cvt)" "v_cvt<cvt_operands>\t%0, %1" [(set_attr "type" "vop1") (set_attr "length" "8")]) @@ -2894,8 +2895,9 @@ [(set (match_operand:VCVT_IMODE 0 "register_operand" "= v") (cvt_op:VCVT_IMODE (match_operand:VCVT_FMODE 1 "gcn_alu_operand" "vSvB")))] - "gcn_valid_cvt_p (<VCVT_FMODE:MODE>mode, <VCVT_IMODE:MODE>mode, - <cvt_name>_cvt)" + "MODE_VF (<VCVT_IMODE:MODE>mode) == MODE_VF (<VCVT_FMODE:MODE>mode) + && gcn_valid_cvt_p (<VCVT_FMODE:MODE>mode, <VCVT_IMODE:MODE>mode, + <cvt_name>_cvt)" "v_cvt<cvt_operands>\t%0, %1" [(set_attr "type" "vop1") (set_attr "length" "8")]) diff --git a/gcc/config/gcn/gcn.h b/gcc/config/gcn/gcn.h index 318256c..38f7212 100644 --- a/gcc/config/gcn/gcn.h +++ b/gcc/config/gcn/gcn.h @@ -678,3 +678,27 @@ enum gcn_builtin_codes /* Trampolines */ #define TRAMPOLINE_SIZE 36 #define TRAMPOLINE_ALIGNMENT 64 + +/* MD Optimization. + The following are intended to be obviously constant at compile time to + allow genconditions to eliminate bad patterns at compile time. */ +#define MODE_VF(M) \ + ((M == V64QImode || M == V64HImode || M == V64HFmode || M == V64SImode \ + || M == V64SFmode || M == V64DImode || M == V64DFmode) \ + ? 64 \ + : (M == V32QImode || M == V32HImode || M == V32HFmode || M == V32SImode \ + || M == V32SFmode || M == V32DImode || M == V32DFmode) \ + ? 32 \ + : (M == V16QImode || M == V16HImode || M == V16HFmode || M == V16SImode \ + || M == V16SFmode || M == V16DImode || M == V16DFmode) \ + ? 16 \ + : (M == V8QImode || M == V8HImode || M == V8HFmode || M == V8SImode \ + || M == V8SFmode || M == V8DImode || M == V8DFmode) \ + ? 8 \ + : (M == V4QImode || M == V4HImode || M == V4HFmode || M == V4SImode \ + || M == V4SFmode || M == V4DImode || M == V4DFmode) \ + ? 4 \ + : (M == V2QImode || M == V2HImode || M == V2HFmode || M == V2SImode \ + || M == V2SFmode || M == V2DImode || M == V2DFmode) \ + ? 2 \ + : 1) |