diff options
| author | Andrew Pinski <quic_apinski@quicinc.com> | 2024-02-12 15:48:48 -0800 |
|---|---|---|
| committer | Andrew Pinski <quic_apinski@quicinc.com> | 2024-04-27 17:15:07 -0700 |
| commit | f91569e779041e2723be23d31c2a79f1861efc7f (patch) | |
| tree | c742efb74478c08c1227594bbef006ae8a867b5c /gcc | |
| parent | 140124ad54eef88ca87909f63aedc8aaeacefc65 (diff) | |
| download | gcc-f91569e779041e2723be23d31c2a79f1861efc7f.zip gcc-f91569e779041e2723be23d31c2a79f1861efc7f.tar.gz gcc-f91569e779041e2723be23d31c2a79f1861efc7f.tar.bz2 | |
aarch64: Use vec_perm_indices::new_shrunk_vector in aarch64_evpc_reencode
While working on PERM related stuff, I can across that aarch64_evpc_reencode
was manually figuring out if we shrink the perm indices instead of
using vec_perm_indices::new_shrunk_vector; shrunk was added after reencode
was added.
Built and tested for aarch64-linux-gnu with no regressions.
gcc/ChangeLog:
PR target/113822
* config/aarch64/aarch64.cc (aarch64_evpc_reencode): Use
vec_perm_indices::new_shrunk_vector instead of manually
going through the indices.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64.cc | 24 |
1 files changed, 5 insertions, 19 deletions
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index a4b7db6..662ff5a 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -25574,7 +25574,6 @@ static bool aarch64_evpc_reencode (struct expand_vec_perm_d *d) { expand_vec_perm_d newd; - unsigned HOST_WIDE_INT nelt; if (d->vec_flags != VEC_ADVSIMD) return false; @@ -25589,24 +25588,10 @@ aarch64_evpc_reencode (struct expand_vec_perm_d *d) if (new_mode == word_mode) return false; - /* to_constant is safe since this routine is specific to Advanced SIMD - vectors. */ - nelt = d->perm.length ().to_constant (); - - vec_perm_builder newpermconst; - newpermconst.new_vector (nelt / 2, nelt / 2, 1); + vec_perm_indices newpermindices; - /* Convert the perm constant if we can. Require even, odd as the pairs. */ - for (unsigned int i = 0; i < nelt; i += 2) - { - poly_int64 elt0 = d->perm[i]; - poly_int64 elt1 = d->perm[i + 1]; - poly_int64 newelt; - if (!multiple_p (elt0, 2, &newelt) || maybe_ne (elt0 + 1, elt1)) - return false; - newpermconst.quick_push (newelt.to_constant ()); - } - newpermconst.finalize (); + if (!newpermindices.new_shrunk_vector (d->perm, 2)) + return false; newd.vmode = new_mode; newd.vec_flags = VEC_ADVSIMD; @@ -25618,7 +25603,8 @@ aarch64_evpc_reencode (struct expand_vec_perm_d *d) newd.testing_p = d->testing_p; newd.one_vector_p = d->one_vector_p; - newd.perm.new_vector (newpermconst, newd.one_vector_p ? 1 : 2, nelt / 2); + newd.perm.new_vector (newpermindices.encoding (), newd.one_vector_p ? 1 : 2, + newpermindices.nelts_per_input ()); return aarch64_expand_vec_perm_const_1 (&newd); } |