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authorYunQiang Su <syq@gcc.gnu.org>2024-06-28 16:11:35 +0800
committerYunQiang Su <syq@gcc.gnu.org>2024-07-05 15:52:38 +0800
commitf1437b96029d78e72bd987997f5303e29ebbb9f0 (patch)
treecd31f1989938a55b473f7b1eb41ad00db0ef10f4 /gcc
parent7eb8b65780d9dc3e266056383279b00d5e152bea (diff)
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MIPS/testsuite: Fix umips-save-restore-1.c
With some recent optimization, -O1/-O2/-O3 can archive almost same performace/size by stack load/store. Thus lwm/swm will save/store less callee-saved register. In fact only $16 is saved with swm. To be sure that this optimization does exist, let's add 2 more function calls. So that lwm/swm can be much more profitable. If we add only once more, -O1 will still use stack load/store. gcc/testsuite * gcc.target/mips/umips-save-restore-1.c: Be sure lwm/swm are used for more callee-saved registers with addtional 2 more function calls.
Diffstat (limited to 'gcc')
-rw-r--r--gcc/testsuite/gcc.target/mips/umips-save-restore-1.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/gcc/testsuite/gcc.target/mips/umips-save-restore-1.c b/gcc/testsuite/gcc.target/mips/umips-save-restore-1.c
index ff1ea4b..0e2c4dc 100644
--- a/gcc/testsuite/gcc.target/mips/umips-save-restore-1.c
+++ b/gcc/testsuite/gcc.target/mips/umips-save-restore-1.c
@@ -7,12 +7,14 @@ int bar (int, int, int, int, int);
MICROMIPS int
foo (int n, int a, int b, int c, int d)
{
- int i, j;
+ int i, j, k, l;
i = bar (n, a, b, c, d);
j = bar (n, a, b, c, d);
- return i + j;
+ k = bar (n, a, b, c, d);
+ l = bar (n, a, b, c, d);
+ return i + j + k + l;
}
-/* { dg-final { scan-assembler "\tswm\t\\\$16-\\\$2(0|1),\\\$31" } } */
-/* { dg-final { scan-assembler "\tlwm\t\\\$16-\\\$2(0|1),\\\$31" } } */
+/* { dg-final { scan-assembler "\tswm\t\\\$16-\\\$2(2|3),\\\$31" } } */
+/* { dg-final { scan-assembler "\tlwm\t\\\$16-\\\$2(2|3),\\\$31" } } */