Daily bump.

3 files changed, 73 insertions, 1 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cddc596..caeb1ee 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,42 @@
+2024-07-06  Jeff Law  <jlaw@ventanamicro.com>
+
+	* config/riscv/bitmanip.md (bset splitters): Turn into define_and_splits.
+	Don't depend on combine splitting the "andn with constant" form.
+	(bset, binv, bclr with masked bit position): New patterns.
+
+2024-07-06  Jeff Law  <jlaw@ventanamicro.com>
+
+	* config/sh/sh.md (adddi3): Only allow matching when we can
+	still create new pseudos.
+	(subdi3, *rotcl, *rotcr, *rotcr_neg_t, negdi2): Likewise.
+	(abs<mode>2, negabs<mode>2, negdi_cond): Likewise.
+	(*swapbisi2_and_shl8, *swapbhisi2, *movsi_index_disp_load): Likewise.
+	(*movhi_index_disp_load, *mov<mode>index_disp_store): Likewise.
+	(*mov_t_msb_neg, *negt_msb, clipu_one): Likewise.
+
+2024-07-06  Georg-Johann Lay  <avr@gjlay.de>
+
+	* config/avr/avr.md: Also split with avr_split_tiny_move()
+	for non-AVR_TINY.
+	* config/avr/avr.cc (avr_split_tiny_move): Don't change memory
+	references with base regs that can do PLUS addressing.
+	(avr_out_lpm_no_lpmx) [POST_INC]: Don't output final ADIW when the
+	address register is unused after.
+
+2024-07-06  Eric Botcazou  <ebotcazou@adacore.com>
+
+	PR target/115591
+	* config/riscv/riscv.cc (riscv_valid_lo_sum_p): Add missing test on
+	tree_fits_uhwi_p before calling tree_to_uhwi.
+
+2024-07-06  Roger Sayle  <roger@nextmovesoftware.com>
+
+	PR target/115751
+	* config/i386/i386-expand.cc (ix86_expand_ternlog): Avoid use of
+	force_reg to "reload" non-register operands, as these may contain
+	vec_duplicate (broadcast) operands that aren't supported by
+	force_reg.  Use (safer) gen_reg_rtx and emit_move instead.
+
 2024-07-05  Iain Sandoe  <iain@sandoe.co.uk>
 
 	* config/i386/i386.cc (ix86_cannot_copy_insn_p): New.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index d97996c..391dc0b 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20240706
+20240707
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e12bee6..d311464 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,36 @@
+2024-07-06  Jeff Law  <jlaw@ventanamicro.com>
+
+	* gcc.target/riscv/binv-for-simode-1.c: New test.
+	* gcc.target/riscv/bset-for-simode-1.c: New test.
+	* gcc.target/riscv/bclr-for-simode-1.c: New test.
+
+2024-07-06  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR testsuite/52641
+	* gcc.dg/analyzer/torture/boxed-ptr-1.c: Requires size24plus.
+	* gcc.dg/analyzer/torture/pr102692.c: Use intptr_t instead of long.
+	* gcc.dg/ipa/pr102714.c: Use uintptr_t instead of unsigned long.
+	* gcc.dg/torture/pr115387-1.c: Same.
+	* gcc.dg/torture/pr113895-1.c : Same.
+	* gcc.dg/ipa/pr108007.c: Require int32plus.
+	* gcc.dg/ipa/pr109318.c: Same.
+	* gcc.dg/ipa/pr96040.c: Use size_t instead of unsigned long.
+	* gcc.dg/torture/pr113126.c: Use vectors of same dimension.
+	* gcc.dg/tree-ssa/builtin-sprintf-9.c: Requires double64.
+	* gcc.dg/spellcheck-inttypes.c [avr]: Avoid include of inttypes.h.
+	* gcc.dg/analyzer/torture/pr104159.c [avr]: Skip.
+	* gcc.dg/torture/pr84682-2.c [avr]: Skip.
+	* gcc.dg/wtr-conversion-1.c [avr]: Remove avr selector since
+	long double is a 64-bit type by now.
+
+2024-07-06  Georg-Johann Lay  <avr@gjlay.de>
+
+	* gcc.target/avr/torture/fuse-add.c: New test.
+
+2024-07-06  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* gnat.dg/array41.ads, gnat.dg/array41.adb: New test.
+
 2024-07-05  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
 
 	* gfortran.dg/ieee/signaling_2.f90: Adjust test.