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| author | Pan Li <pan2.li@intel.com> | 2024-05-09 10:56:46 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2024-05-09 18:48:11 +0800 |
| commit | b1520d2260c5e0cfcd7a4354fab70f66e2912ff2 (patch) | |
| tree | 8a15499b0435918c508885da602e2a3f280f4c84 /gcc | |
| parent | de0b40ac5be8977a6bee8860f67d45011642f1a2 (diff) | |
| download | gcc-b1520d2260c5e0cfcd7a4354fab70f66e2912ff2.zip gcc-b1520d2260c5e0cfcd7a4354fab70f66e2912ff2.tar.gz gcc-b1520d2260c5e0cfcd7a4354fab70f66e2912ff2.tar.bz2 | |
RISC-V: Make full-vec-move1.c test robust for optimization
During investigate the support of early break autovec, we notice
the test full-vec-move1.c will be optimized to 'return 0;' in main
function body. Because somehow the value of V type is compiler
time constant, and then the second loop will be considered as
assert (true).
Thus, the ccp4 pass will eliminate these stmt and just return 0.
typedef int16_t V __attribute__((vector_size (128)));
int main ()
{
V v;
for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
(v)[i] = i;
V res = v;
for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
assert (res[i] == i); // will be optimized to assert (true)
}
This patch would like to introduce a extern function to use the res[i]
that get rid of the ccp4 optimization.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c:
Introduce extern func use to get rid of ccp4 optimization.
Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c index d73bad4..fae2ae9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c @@ -2,11 +2,12 @@ /* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=zvl" } */ #include <stdint-gcc.h> -#include <assert.h> /* This would cause us to emit a vl1r.v for VNx4HImode even when the hardware vector size vl > 64. */ +extern int16_t test_element (int16_t); + typedef int16_t V __attribute__((vector_size (128))); int main () @@ -14,9 +15,10 @@ int main () V v; for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++) (v)[i] = i; + V res = v; for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++) - assert (res[i] == i); + test_element (res[i]); } /* { dg-final { scan-assembler-not {vl[1248]r.v} } } */ |