RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 4

This patch would like to add test cases for the unsigned vector
.SAT_TRUNC form 4.  Aka:

Form 4:
  #define DEF_VEC_SAT_U_TRUNC_FMT_4(NT, WT)                             \
  void __attribute__((noinline))                                        \
  vec_sat_u_trunc_##NT##_##WT##_fmt_4 (NT *out, WT *in, unsigned limit) \
  {                                                                     \
    unsigned i;                                                         \
    for (i = 0; i < limit; i++)                                         \
      {                                                                 \
        bool not_overflow = in[i] <= (WT)(NT)(-1);                      \
        out[i] = ((NT)in[i]) | (NT)((NT)not_overflow - 1);              \
      }                                                                 \
  }

DEF_VEC_SAT_U_TRUNC_FMT_4 (uint32_t, uint64_t)

The below test is passed for this patch.
* The rv64gcv regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-19.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-20.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-21.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-22.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-23.c: New test.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-24.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

13 files changed, 236 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
new file mode 100644
index 0000000..a80cefe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../vec_sat_arith.h"
+
+/*
+** vec_sat_u_trunc_uint8_t_uint16_t_fmt_4:
+** ...
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
+** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** ...
+*/
+DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
new file mode 100644
index 0000000..9a4d261
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../vec_sat_arith.h"
+
+/*
+** vec_sat_u_trunc_uint8_t_uint32_t_fmt_4:
+** ...
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
+** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma
+** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** ...
+*/
+DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c
new file mode 100644
index 0000000..5f0b71b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../vec_sat_arith.h"
+
+/*
+** vec_sat_u_trunc_uint8_t_uint64_t_fmt_4:
+** ...
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
+** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma
+** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** ...
+*/
+DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c
new file mode 100644
index 0000000..059758b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../vec_sat_arith.h"
+
+/*
+** vec_sat_u_trunc_uint16_t_uint32_t_fmt_4:
+** ...
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
+** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** ...
+*/
+DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c
new file mode 100644
index 0000000..6e094d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../vec_sat_arith.h"
+
+/*
+** vec_sat_u_trunc_uint16_t_uint64_t_fmt_4:
+** ...
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
+** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** ...
+*/
+DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c
new file mode 100644
index 0000000..707b20b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../vec_sat_arith.h"
+
+/*
+** vec_sat_u_trunc_uint32_t_uint64_t_fmt_4:
+** ...
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
+** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** vse32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** ...
+*/
+DEF_VEC_SAT_U_TRUNC_FMT_4 (uint32_t, uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-19.c
new file mode 100644
index 0000000..4e387d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-19.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T1 uint8_t
+#define T2 uint16_t
+
+DEF_VEC_SAT_U_TRUNC_FMT_1_WRAP(T1, T2)
+
+#define T                     TEST_UNARY_STRUCT_DECL(T1, T2)
+#define DATA                  TEST_UNARY_DATA_WRAP(T1, T2)
+#define RUN_UNARY(out, in, N) RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(T1, T2, out, in, N)
+
+#include "vec_sat_unary_vv_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-20.c
new file mode 100644
index 0000000..a51ad60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-20.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T1 uint8_t
+#define T2 uint32_t
+
+DEF_VEC_SAT_U_TRUNC_FMT_1_WRAP(T1, T2)
+
+#define T                     TEST_UNARY_STRUCT_DECL(T1, T2)
+#define DATA                  TEST_UNARY_DATA_WRAP(T1, T2)
+#define RUN_UNARY(out, in, N) RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(T1, T2, out, in, N)
+
+#include "vec_sat_unary_vv_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-21.c
new file mode 100644
index 0000000..90a12c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-21.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T1 uint8_t
+#define T2 uint64_t
+
+DEF_VEC_SAT_U_TRUNC_FMT_1_WRAP(T1, T2)
+
+#define T                     TEST_UNARY_STRUCT_DECL(T1, T2)
+#define DATA                  TEST_UNARY_DATA_WRAP(T1, T2)
+#define RUN_UNARY(out, in, N) RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(T1, T2, out, in, N)
+
+#include "vec_sat_unary_vv_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-22.c
new file mode 100644
index 0000000..3e7a7ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-22.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T1 uint16_t
+#define T2 uint32_t
+
+DEF_VEC_SAT_U_TRUNC_FMT_1_WRAP(T1, T2)
+
+#define T                     TEST_UNARY_STRUCT_DECL(T1, T2)
+#define DATA                  TEST_UNARY_DATA_WRAP(T1, T2)
+#define RUN_UNARY(out, in, N) RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(T1, T2, out, in, N)
+
+#include "vec_sat_unary_vv_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-23.c
new file mode 100644
index 0000000..ffb9e6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-23.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T1 uint16_t
+#define T2 uint64_t
+
+DEF_VEC_SAT_U_TRUNC_FMT_1_WRAP(T1, T2)
+
+#define T                     TEST_UNARY_STRUCT_DECL(T1, T2)
+#define DATA                  TEST_UNARY_DATA_WRAP(T1, T2)
+#define RUN_UNARY(out, in, N) RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(T1, T2, out, in, N)
+
+#include "vec_sat_unary_vv_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-24.c
new file mode 100644
index 0000000..82396f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-24.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T1 uint32_t
+#define T2 uint64_t
+
+DEF_VEC_SAT_U_TRUNC_FMT_1_WRAP(T1, T2)
+
+#define T                     TEST_UNARY_STRUCT_DECL(T1, T2)
+#define DATA                  TEST_UNARY_DATA_WRAP(T1, T2)
+#define RUN_UNARY(out, in, N) RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(T1, T2, out, in, N)
+
+#include "vec_sat_unary_vv_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
index b662249..f28cb7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
@@ -432,6 +432,19 @@ vec_sat_u_trunc_##NT##_##WT##_fmt_3 (NT *out, WT *in, unsigned limit) \
 }
 #define DEF_VEC_SAT_U_TRUNC_FMT_3_WRAP(NT, WT) DEF_VEC_SAT_U_TRUNC_FMT_3(NT, WT)
 
+#define DEF_VEC_SAT_U_TRUNC_FMT_4(NT, WT)                             \
+void __attribute__((noinline))                                        \
+vec_sat_u_trunc_##NT##_##WT##_fmt_4 (NT *out, WT *in, unsigned limit) \
+{                                                                     \
+  unsigned i;                                                         \
+  for (i = 0; i < limit; i++)                                         \
+    {                                                                 \
+      bool not_overflow = in[i] <= (WT)(NT)(-1);                      \
+      out[i] = ((NT)in[i]) | (NT)((NT)not_overflow - 1);              \
+    }                                                                 \
+}
+#define DEF_VEC_SAT_U_TRUNC_FMT_4_WRAP(NT, WT) DEF_VEC_SAT_U_TRUNC_FMT_4(NT, WT)
+
 #define RUN_VEC_SAT_U_TRUNC_FMT_1(NT, WT, out, in, N) \
   vec_sat_u_trunc_##NT##_##WT##_fmt_1 (out, in, N)
 #define RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(NT, WT, out, in, N) \
@@ -447,4 +460,9 @@ vec_sat_u_trunc_##NT##_##WT##_fmt_3 (NT *out, WT *in, unsigned limit) \
 #define RUN_VEC_SAT_U_TRUNC_FMT_3_WRAP(NT, WT, out, in, N) \
   RUN_VEC_SAT_U_TRUNC_FMT_3(NT, WT, out, in, N)
 
+#define RUN_VEC_SAT_U_TRUNC_FMT_4(NT, WT, out, in, N) \
+  vec_sat_u_trunc_##NT##_##WT##_fmt_4 (out, in, N)
+#define RUN_VEC_SAT_U_TRUNC_FMT_4_WRAP(NT, WT, out, in, N) \
+  RUN_VEC_SAT_U_TRUNC_FMT_4(NT, WT, out, in, N)
+
 #endif