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| author | Segher Boessenkool <segher@kernel.crashing.org> | 2019-06-05 01:29:31 +0200 |
|---|---|---|
| committer | Segher Boessenkool <segher@gcc.gnu.org> | 2019-06-05 01:29:31 +0200 |
| commit | 7858932efcc352a8ca2966f48c4c3b9c58c64022 (patch) | |
| tree | d67dddb4624b41f243b6ea1daa40360ed44e92fd /gcc | |
| parent | 012f609e02aa915808883cda0159cb59751b37f4 (diff) | |
| download | gcc-7858932efcc352a8ca2966f48c4c3b9c58c64022.zip gcc-7858932efcc352a8ca2966f48c4c3b9c58c64022.tar.gz gcc-7858932efcc352a8ca2966f48c4c3b9c58c64022.tar.bz2 | |
rs6000: Simplify <VSa> for VSX_W
When used in VSX_W, <VSa> is always just "wa".
* config/rs6000/vsx.md: Replace all <VSa> that are used with VSX_W
with just "wa".
From-SVN: r271930
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 32 |
2 files changed, 21 insertions, 16 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8353f04..00ca70e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2019-06-04 Segher Boessenkool <segher@kernel.crashing.org> + * config/rs6000/vsx.md: Replace all <VSa> that are used with VSX_W + with just "wa". + +2019-06-04 Segher Boessenkool <segher@kernel.crashing.org> + * config/rs6000/vsx.md (define_mode_attr VSr2): Delete. (rest of file): Replace all <VSa>, <VSr>, <VSr2>, and <VSr3> that are used with VSX_B, VSX_D, or VSX_F, with just "wa". diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 11e50bf..d349091 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -468,7 +468,7 @@ (set_attr "length" "8")]) (define_insn_and_split "*vsx_le_perm_load_<mode>" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") (match_operand:VSX_W 1 "indexed_or_indirect_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" @@ -705,7 +705,7 @@ (define_insn "*vsx_le_perm_store_<mode>" [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "=Z") - (match_operand:VSX_W 1 "vsx_register_operand" "+<VSa>"))] + (match_operand:VSX_W 1 "vsx_register_operand" "+wa"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" [(set_attr "type" "vecstore") @@ -2983,9 +2983,9 @@ [(set_attr "type" "vecperm")]) (define_insn "*vsx_xxpermdi4_le_<mode>" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") (vec_select:VSX_W - (match_operand:VSX_W 1 "vsx_register_operand" "<VSa>") + (match_operand:VSX_W 1 "vsx_register_operand" "wa") (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)" @@ -3032,7 +3032,7 @@ [(set_attr "type" "vecload")]) (define_insn "*vsx_lxvd2x4_le_<mode>" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") (vec_select:VSX_W (match_operand:VSX_W 1 "memory_operand" "Z") (parallel [(const_int 2) (const_int 3) @@ -3083,7 +3083,7 @@ (define_insn "*vsx_stxvd2x4_le_<mode>" [(set (match_operand:VSX_W 0 "memory_operand" "=Z") (vec_select:VSX_W - (match_operand:VSX_W 1 "vsx_register_operand" "<VSa>") + (match_operand:VSX_W 1 "vsx_register_operand" "wa") (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode) && !TARGET_P9_VECTOR" @@ -4156,10 +4156,10 @@ ;; V4SF/V4SI splat from a vector element (define_insn "vsx_xxspltw_<mode>" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") (vec_duplicate:VSX_W (vec_select:<VS_scalar> - (match_operand:VSX_W 1 "vsx_register_operand" "<VSa>") + (match_operand:VSX_W 1 "vsx_register_operand" "wa") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "n")]))))] "VECTOR_MEM_VSX_P (<MODE>mode)" @@ -4172,8 +4172,8 @@ [(set_attr "type" "vecperm")]) (define_insn "vsx_xxspltw_<mode>_direct" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>") - (unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "<VSa>") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") + (unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "wa") (match_operand:QI 2 "u5bit_cint_operand" "i")] UNSPEC_VSX_XXSPLTW))] "VECTOR_MEM_VSX_P (<MODE>mode)" @@ -4208,11 +4208,11 @@ ;; V4SF/V4SI interleave (define_insn "vsx_xxmrghw_<mode>" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa,?<VSa>") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") (vec_select:VSX_W (vec_concat:<VS_double> - (match_operand:VSX_W 1 "vsx_register_operand" "wa,<VSa>") - (match_operand:VSX_W 2 "vsx_register_operand" "wa,<VSa>")) + (match_operand:VSX_W 1 "vsx_register_operand" "wa") + (match_operand:VSX_W 2 "vsx_register_operand" "wa")) (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "VECTOR_MEM_VSX_P (<MODE>mode)" @@ -4225,11 +4225,11 @@ [(set_attr "type" "vecperm")]) (define_insn "vsx_xxmrglw_<mode>" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa,?<VSa>") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") (vec_select:VSX_W (vec_concat:<VS_double> - (match_operand:VSX_W 1 "vsx_register_operand" "wa,<VSa>") - (match_operand:VSX_W 2 "vsx_register_operand" "wa,?<VSa>")) + (match_operand:VSX_W 1 "vsx_register_operand" "wa") + (match_operand:VSX_W 2 "vsx_register_operand" "wa")) (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "VECTOR_MEM_VSX_P (<MODE>mode)" |