Daily bump.

6 files changed, 410 insertions, 1 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1c44892..94b6069 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,167 @@
+2024-07-16  Andrew MacLeod  <amacleod@redhat.com>
+
+	PR tree-optimization/115951
+	* range-op-ptr.cc (operator_equal::fold_range): Return a boolean
+	range with the requested type.
+	(operator_not_equal::fold_range): Likewise.
+	(operator_lt::fold_range): Likewise.
+	(operator_le::fold_range): Likewise.
+	(operator_gt::fold_range): Likewise.
+	(operator_ge::fold_range): Likewise.
+
+2024-07-16  Iain Sandoe  <iain@sandoe.co.uk>
+
+	PR c++/115434
+	PR c++/110871
+	PR c++/110872
+	* gimplify.cc (struct gimplify_ctx): Add a flag to show we are
+	expending a handler.
+	(gimplify_expr): When we are expanding a handler, and the body
+	transforms might have re-written DECL_RESULT into a gimple var,
+	ensure that hander references to DECL_RESULT are also re-written
+	to refer to the gimple var.  When we are processing an EH_ELSE
+	expression, then add it if either of the cleanup slots is in
+	use.
+
+2024-07-16  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR rtl-optimization/115929
+	* rtl-ssa/insns.cc (function_info::remove_insn): Remove an
+	order_node from the instruction as well as from the splay tree.
+
+2024-07-16  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR rtl-optimization/115901
+	* recog.cc (insn_propagation::apply_to_rvalue_1): Restrict
+	paradoxical mode punning to cases where "to" is constant.
+
+2024-07-16  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR rtl-optimization/115891
+	* rtl-ssa/changes.cc (find_clobbered_access): New function.
+	(recog_level2): Use it to check for overlap between input
+	registers and hard-coded clobbers.  Conditionally reset
+	recog_data.insn after changing the insn code.
+
+2024-07-16  Georg-Johann Lay  <avr@gjlay.de>
+
+	* config/avr/avr.cc (avr_out_minus): Assimilate into...
+	(avr_out_plus_ext): ...this new function.
+	(avr_adjust_insn_length) [ADJUST_LEN_PLUS_EXT]: Handle case.
+	(avr_rtx_costs_1) [PLUS, MINUS]: Adjust RTX costs.
+	* config/avr/avr.md (adjust_len) <plus_ext>: Add new attribute value.
+	(*addpsi3_zero_extend.hi_split): Assimilate...
+	(*addpsi3_zero_extend.qi_split): Assimilate...
+	(*addsi3_zero_extend_split): Assimilate...
+	(*addsi3_zero_extend.hi_split): Assimilate...
+	(*addpsi3_sign_extend.hi_split): Assimilate...
+	(*addhi3.sign_extend1_split): Assimilate...
+	(*add<PSISI:mode>3.<code>.<QIPSI:mode>_split): ...into this
+	new insn-and-split.
+	(*addpsi3_zero_extend.hi): Assimilate...
+	(*addpsi3_zero_extend.qi): Assimilate...
+	(*addsi3_zero_extend): Assimilate...
+	(*addsi3_zero_extend.hi): Assimilate...
+	(*addpsi3_sign_extend.hi): Assimilate...
+	(*addhi3.sign_extend1): Assimilate...
+	(*add<PSISI:mode>3.<code>.<QIPSI:mode>): ...into this new insn.
+	(*subpsi3_sign_extend.hi_split): Assimilate...
+	(*subhi3.sign_extend2_split): Assimilate...
+	(*sub<HISI:mode>3.zero_extend.<QIPSI:mode>_split): Assimilate...
+	(*sub<HISI:mode>3.<code><QIPSI:mode>_split): ...into this new
+	insn-and-split.
+	(*subpsi3_sign_extend.hi): Assimilate...
+	(*subhi3.sign_extend2): Assimilate...
+	(*sub<HISI:mode>3.zero_extend.<QIPSI:mode>): Assimilate...
+	(*sub<HISI:mode>3.<code>.<QIPSI:mode>): ...into this new insn.
+	(*sub<HISI:mode>3.zero_extend.<QIPSI:mode>): Use avr_out_plus_ext
+	for asm out.
+	* config/avr/avr-protos.h (avr_out_minus): Remove.
+	(avr_out_plus_ext): New proto.
+
+2024-07-16  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/115841
+	* tree-vect-loop.cc (vect_transform_cycle_phi): Correctly
+	place the partial vector reduction for the accumulator
+	re-use when the main loop cannot be skipped but the
+	epilogue can.
+
+2024-07-16  Georg-Johann Lay  <avr@gjlay.de>
+
+	* config/avr/avr-protos.h (avr_emit_xior_with_shift): New proto.
+	* config/avr/avr.cc (avr_emit_xior_with_shift): New function.
+	* config/avr/avr.md (any_lshift): New code iterator.
+	(*<xior:code><mode>.<any_lshift:code>): New insn-and-split.
+	(<code><HISI:mode><QIPSI:mode>.0): Replaces...
+	(*<code_stdname><mode>qi.byte0): ...this one.
+	(*<xior:code><HISI:mode><QIPSI:mode>.<any_lshift:code>): Replaces...
+	(*<code_stdname><mode>qi.byte1-3): ...this one.
+
+2024-07-16  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+
+	* config/s390/3931.md (vlbr, vstbr): Remove.
+	* config/s390/s390.md (xdee): Add FPRX2 mapping.
+	* config/s390/vector.md (bhfgq): Add TF mapping.
+
+2024-07-16  Richard Biener  <rguenther@suse.de>
+
+	* config/i386/x86-tune-costs.h (znver5_cost): Update unaligned
+	load and store cost from the aligned costs.
+
+2024-07-16  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+
+	PR target/114189
+	* config/s390/vector.md (V_HW2): Remove.
+	(vcond<V_HW:mode><V_HW2:mode>): Remove.
+	(vcondu<V_HW:mode><V_HW2:mode>): Remove.
+
+2024-07-16  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+
+	* config/s390/vector.md: Enable vcond_mask for 128-bit ops.
+
+2024-07-16  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+
+	* config/s390/vector.md (V_HW): Enable V1TI unconditionally and
+	add TI.
+	(vec_cmpu<VIT_HW:mode><VIT_HW:mode>): Add 128-bit integer
+	variants.
+	(*vec_cmpeq<mode><mode>_nocc_emu): Emulate operation.
+	(*vec_cmpgt<mode><mode>_nocc_emu): Emulate operation.
+	(*vec_cmpgtu<mode><mode>_nocc_emu): Emulate operation.
+
+2024-07-16  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/115843
+	* tree-vect-loop-manip.cc
+	(vect_set_loop_condition_partial_vectors_avx512): Properly
+	bias the shift of the initial mask for alignment peeling.
+
+2024-07-16  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/115843
+	* config/i386/x86-tune-costs.h (znver4_cost): Update unaligned
+	load and store cost from the aligned costs.
+
+2024-07-16  Roger Sayle  <roger@nextmovesoftware.com>
+	    Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/114661
+	* match.pd ((X*C1)|(X*C2) to X*(C1+C2)): Allow optional useless
+	type conversions around multiplications, such as those inserted
+	by this transformation.
+
+2024-07-16  Hu, Lin1  <lin1.hu@intel.com>
+
+	PR target/107432
+	* config/i386/sse.md
+	(PMOV_SRC_MODE_3_AVX2): Add TARGET_AVX2 for V4DI and V8SI.
+	(PMOV_SRC_MODE_4): Add TARGET_AVX2 for V4DI.
+	(trunc<mode><pmov_dst_3_lower>2): Change constraint from TARGET_AVX2 to
+	TARGET_SSSE3.
+	(trunc<mode><pmov_dst_4_lower>2): Ditto.
+	(truncv2div2si2): Change constraint from TARGET_AVX2 to TARGET_SSE.
+
 2024-07-16  Jeff Law  <jlaw@ventanamicro.com>
 
 	* ext-dce.cc (ext_dce_process_uses): Simplify control flow and fix
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e63e190..5961a7c 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20240716
+20240717
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 4b0ed7b..af628e0 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,40 @@
+2024-07-16  Nina Ranns  <dinka.ranns@gmail.com>
+
+	PR c++/110159
+	* cp-tree.h (init_terminate_fn): Declaration of a new function.
+	* decl.cc (cxx_init_decl_processing): If contracts are enabled,
+	call init_terminate_fn.
+	* except.cc (init_exception_processing): Function refactored to
+	call init_terminate_fn.
+	(init_terminate_fn): Added new function that initializes
+	terminate_fn if	it hasn't already been initialised.
+
+2024-07-16  Iain Sandoe  <iain@sandoe.co.uk>
+
+	PR c++/115434
+	PR c++/110871
+	PR c++/110872
+	* constexpr.cc (cxx_eval_constant_expression): Handle EH_ELSE_EXPR.
+	* contracts.cc (finish_contract_attribute): Remove excess line.
+	(build_contract_condition_function): Post condition handlers are
+	void now.
+	(emit_postconditions_cleanup): Remove.
+	(emit_postconditions): New.
+	(add_pre_condition_fn_call): New.
+	(add_post_condition_fn_call): New.
+	(apply_preconditions): New.
+	(apply_postconditions): New.
+	(maybe_apply_function_contracts): New.
+	(apply_postcondition_to_return): Remove.
+	* contracts.h (apply_postcondition_to_return): Remove.
+	(maybe_apply_function_contracts): Add.
+	* coroutines.cc (coro_build_actor_or_destroy_function): Do not
+	copy contracts to coroutine helpers.
+	* decl.cc (finish_function): Handle wrapping a possibly
+	transformed function body in contract checks.
+	* typeck.cc (check_return_expr): Remove handling of post
+	conditions on return expressions.
+
 2024-07-15  Patrick Palka  <ppalka@redhat.com>
 
 	PR c++/115897
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 775502c..475c155 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,18 @@
+2024-07-16  Paul Thomas  <pault@gcc.gnu.org>
+
+	PR fortran/84868
+	* simplify.cc (gfc_simplify_len_trim): If the argument is an
+	element of a parameter array, simplify all the elements and
+	build a new parameter array to hold the result, after checking
+	that it doesn't already exist.
+	* trans-expr.cc (gfc_get_interface_mapping_array) if a string
+	length is available, use it for the typespec.
+	(gfc_add_interface_mapping): Supply the se string length.
+
+2024-07-16  Prathamesh Kulkarni  <prathameshk@nvidia.com>
+
+	* trans-expr.cc (gfc_trans_zero_assign): Handle allocatable arrays.
+
 2024-07-13  Mikael Morin  <mikael@gcc.gnu.org>
 
 	* trans-intrinsic.cc (gfc_conv_intrinsic_minmaxloc): Add the
diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog
index b48e119..0d77aad 100644
--- a/gcc/m2/ChangeLog
+++ b/gcc/m2/ChangeLog
@@ -1,3 +1,24 @@
+2024-07-16  Gaius Mulley  <gaiusmod2@gmail.com>
+
+	PR modula2/115957
+	* gm2-compiler/M2StackAddress.mod (PopAddress): Detect tail=NIL
+	and generate an internal error.
+	* gm2-compiler/PCBuild.bnf (InConstParameter): New variable.
+	(InConstBlock): New variable.
+	(ErrorString): Rewrite using MetaErrorStringT0.
+	(ErrorArrayAt): Rewrite using MetaErrorStringT0.
+	(WarnMissingToken): Use MetaErrorStringT0.
+	(CompilationUnit): Set seenError FALSE.
+	(init): Initialize InConstParameter and InConstBlock.
+	(ConstantDeclaration): Set InConstBlock.
+	(ConstSetOrQualidentOrFunction): Call CheckNotVar if not
+	InConstParameter and InConstBlock.
+	(ConstActualParameters): Set InConstParameter TRUE and restore
+	value at the end.
+	* gm2-compiler/PCSymBuild.def (CheckNotVar): New procedure.
+	Remove all unnecessary export qualified list.
+	* gm2-compiler/PCSymBuild.mod (CheckNotVar): New procedure.
+
 2024-07-12  FX Coudert  <fxcoudert@gmail.com>
 
 	* gm2-gcc/m2linemap.cc (INCLUDE_STRING): Define before
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 5839739..50ccfd3 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,175 @@
+2024-07-16  Nina Ranns  <dinka.ranns@gmail.com>
+
+	PR c++/110159
+	* g++.dg/contracts/pr110159.C: New test.
+
+2024-07-16  Georg-Johann Lay  <avr@gjlay.de>
+
+	* gcc.target/avr/isr-test.h: Attribute ipa implies noinline and noclone.
+	* gcc.target/avr/pr114981-powif.c: Same.
+	* gcc.target/avr/pr114981-powil.c: Same.
+	* gcc.target/avr/pr71676-1.c: Same.
+	* gcc.target/avr/pr71676-2.c: Same.
+	* gcc.target/avr/pr71676-3.c: Same.
+	* gcc.target/avr/pr71676.c: Same.
+	* gcc.target/avr/torture/add-extend.c: Same.
+	* gcc.target/avr/torture/fix-types.h: Same.
+	* gcc.target/avr/torture/fuse-add.c: Same.
+	* gcc.target/avr/torture/get-mem.c: Same.
+	* gcc.target/avr/torture/insv-anyshift-hi.c: Same.
+	* gcc.target/avr/torture/insv-anyshift-si.c: Same.
+	* gcc.target/avr/torture/isr-02-call.c: Same.
+	* gcc.target/avr/torture/isr-03-fixed.c: Same.
+	* gcc.target/avr/torture/pr109650-1.c: Same.
+	* gcc.target/avr/torture/pr109650-2.c: Same.
+	* gcc.target/avr/torture/pr109907-1.c: Same.
+	* gcc.target/avr/torture/pr109907-2.c: Same.
+	* gcc.target/avr/torture/pr114132-2.c: Same.
+	* gcc.target/avr/torture/pr39633.c: Same.
+	* gcc.target/avr/torture/pr51782-1.c: Same.
+	* gcc.target/avr/torture/pr61055.c: Same.
+	* gcc.target/avr/torture/pr61443.c: Same.
+	* gcc.target/avr/torture/pr64331.c: Same.
+	* gcc.target/avr/torture/pr77326.c: Same.
+	* gcc.target/avr/torture/pr83729.c: Same.
+	* gcc.target/avr/torture/pr83801.c: Same.
+	* gcc.target/avr/torture/pr87376.c: Same.
+	* gcc.target/avr/torture/pr88236-pr115726.c: Same.
+	* gcc.target/avr/torture/pr92606.c: Same.
+	* gcc.target/avr/torture/pr98762.c: Same.
+	* gcc.target/avr/torture/sat-hr-plus-minus.c: Same.
+	* gcc.target/avr/torture/sat-k-plus-minus.c: Same.
+	* gcc.target/avr/torture/sat-llk-plus-minus.c: Same.
+	* gcc.target/avr/torture/sat-r-plus-minus.c: Same.
+	* gcc.target/avr/torture/sat-uhr-plus-minus.c: Same.
+	* gcc.target/avr/torture/sat-uk-plus-minus.c: Same.
+	* gcc.target/avr/torture/sat-ullk-plus-minus.c: Same.
+	* gcc.target/avr/torture/sat-ur-plus-minus.c: Same.
+	* gcc.target/avr/torture/set-mem.c: Same.
+	* gcc.target/avr/torture/sub-extend.c: Same.
+	* gcc.target/avr/torture/tiny-progmem.c: Same.
+
+2024-07-16  Iain Sandoe  <iain@sandoe.co.uk>
+
+	PR c++/115434
+	PR c++/110871
+	PR c++/110872
+	* g++.dg/contracts/pr115434.C: New test.
+	* g++.dg/coroutines/pr110871.C: New test.
+	* g++.dg/coroutines/pr110872.C: New test.
+
+2024-07-16  Georg-Johann Lay  <avr@gjlay.de>
+
+	* gcc.target/avr/isr-test.h: Add noipa function attribute
+	to noclone functions.
+	* gcc.target/avr/pr114981-powif.c: Same.
+	* gcc.target/avr/pr114981-powil.c: Same.
+	* gcc.target/avr/pr71676-1.c: Same.
+	* gcc.target/avr/pr71676-2.c: Same.
+	* gcc.target/avr/pr71676-3.c: Same.
+	* gcc.target/avr/pr71676.c: Same.
+	* gcc.target/avr/torture/fix-types.h: Same.
+	* gcc.target/avr/torture/fuse-add.c: Same.
+	* gcc.target/avr/torture/get-mem.c: Same.
+	* gcc.target/avr/torture/insv-anyshift-hi.c: Same.
+	* gcc.target/avr/torture/insv-anyshift-si.c: Same.
+	* gcc.target/avr/torture/isr-02-call.c: Same.
+	* gcc.target/avr/torture/isr-03-fixed.c: Same.
+	* gcc.target/avr/torture/pr109650-1.c: Same.
+	* gcc.target/avr/torture/pr109650-2.c: Same.
+	* gcc.target/avr/torture/pr109907-1.c: Same.
+	* gcc.target/avr/torture/pr109907-2.c: Same.
+	* gcc.target/avr/torture/pr114132-2.c: Same.
+	* gcc.target/avr/torture/pr39633.c: Same.
+	* gcc.target/avr/torture/pr51782-1.c: Same.
+	* gcc.target/avr/torture/pr61055.c: Same.
+	* gcc.target/avr/torture/pr61443.c: Same.
+	* gcc.target/avr/torture/pr64331.c: Same.
+	* gcc.target/avr/torture/pr77326.c: Same.
+	* gcc.target/avr/torture/pr83729.c: Same.
+	* gcc.target/avr/torture/pr83801.c: Same.
+	* gcc.target/avr/torture/pr87376.c: Same.
+	* gcc.target/avr/torture/pr88236-pr115726.c: Same.
+	* gcc.target/avr/torture/pr92606.c: Same.
+	* gcc.target/avr/torture/pr98762.c: Same.
+	* gcc.target/avr/torture/sat-hr-plus-minus.c: Same.
+	* gcc.target/avr/torture/sat-k-plus-minus.c: Same.
+	* gcc.target/avr/torture/sat-llk-plus-minus.c: Same.
+	* gcc.target/avr/torture/sat-r-plus-minus.c: Same.
+	* gcc.target/avr/torture/sat-uhr-plus-minus.c: Same.
+	* gcc.target/avr/torture/sat-uk-plus-minus.c: Same.
+	* gcc.target/avr/torture/sat-ullk-plus-minus.c: Same.
+	* gcc.target/avr/torture/sat-ur-plus-minus.c: Same.
+	* gcc.target/avr/torture/set-mem.c: Same.
+	* gcc.target/avr/torture/tiny-progmem.c: Same.
+
+2024-07-16  Paul Thomas  <pault@gcc.gnu.org>
+
+	PR fortran/84868
+	* gfortran.dg/pr84868.f90: New test.
+
+2024-07-16  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR rtl-optimization/115929
+	* gcc.dg/torture/pr115929-1.c: New test.
+
+2024-07-16  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR rtl-optimization/115901
+	* gcc.dg/torture/pr115901.c: New test.
+
+2024-07-16  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR rtl-optimization/115891
+	* gcc.target/i386/pr115891.c: New test.
+
+2024-07-16  Georg-Johann Lay  <avr@gjlay.de>
+
+	* gcc.target/avr/torture/add-extend.c: New test.
+	* gcc.target/avr/torture/sub-extend.c: New test.
+
+2024-07-16  Gaius Mulley  <gaiusmod2@gmail.com>
+
+	PR modula2/115957
+	* gm2/errors/fail/badconst.mod: New test.
+	* gm2/pim/fail/tinyadr.mod: New test.
+
+2024-07-16  Prathamesh Kulkarni  <prathameshk@nvidia.com>
+
+	* gfortran.dg/array_memset_3.f90: New test.
+
+2024-07-16  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/115841
+	* gcc.dg/vect/pr115841.c: New testcase.
+
+2024-07-16  Paul-Antoine Arras  <parras@baylibre.com>
+
+	* gcc.target/i386/indirect-thunk-extern-1.c: Replace character with
+	invalid encoding with `?`.
+
+2024-07-16  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+
+	* gcc.target/s390/vector/vec-cmp-emu-1.c: New test.
+	* gcc.target/s390/vector/vec-cmp-emu-2.c: New test.
+	* gcc.target/s390/vector/vec-cmp-emu-3.c: New test.
+
+2024-07-16  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/115843
+	* gcc.dg/vect/pr115843.c: New testcase.
+
+2024-07-16  Roger Sayle  <roger@nextmovesoftware.com>
+	    Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/114661
+	* gcc.dg/pr114661.c: New test case.
+
+2024-07-16  Hu, Lin1  <lin1.hu@intel.com>
+
+	PR target/107432
+	* gcc.target/i386/pr107432-10.c: New test.
+
 2024-07-15  Jeff Law  <jlaw@ventanamicro.com>
 
 	* g++.dg/torture/pr115916.C: New test.