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| author | Tamar Christina <tamar.christina@arm.com> | 2024-07-05 12:09:21 +0100 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2024-07-05 12:09:21 +0100 |
| commit | 6ff698106644af39da9e0eda51974fdcd111280d (patch) | |
| tree | 2f96b1146f9f1369f812dfa56565e4d4a73c0d8d /gcc | |
| parent | ae07f62a70ee2d0fdd7d8786122ae6360cfd4ca9 (diff) | |
| download | gcc-6ff698106644af39da9e0eda51974fdcd111280d.zip gcc-6ff698106644af39da9e0eda51974fdcd111280d.tar.gz gcc-6ff698106644af39da9e0eda51974fdcd111280d.tar.bz2 | |
AArch64: remove aarch64_simd_vec_unpack<su>_lo_
The fix for PR18127 reworked the uxtl to zip optimization.
In doing so it undid the changes in aarch64_simd_vec_unpack<su>_lo_ and this now
no longer matches aarch64_simd_vec_unpack<su>_hi_. It still works because the
RTL generated by aarch64_simd_vec_unpack<su>_lo_ overlaps with the general zero
extend RTL and so because that one is listed before the lo pattern recog picks
it instead.
This removes aarch64_simd_vec_unpack<su>_lo_.
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md
(aarch64_simd_vec_unpack<su>_lo_<mode>): Remove.
(vec_unpack<su>_lo_<mode): Simplify.
* config/aarch64/aarch64.cc (aarch64_gen_shareable_zero): Update
comment.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 20 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.cc | 3 |
2 files changed, 5 insertions, 18 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index fd10039..bbeee22 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1904,17 +1904,6 @@ ;; Widening operations. -(define_insn "aarch64_simd_vec_unpack<su>_lo_<mode>" - [(set (match_operand:<VWIDE> 0 "register_operand" "=w") - (ANY_EXTEND:<VWIDE> (vec_select:<VHALF> - (match_operand:VQW 1 "register_operand" "w") - (match_operand:VQW 2 "vect_par_cnst_lo_half" "") - )))] - "TARGET_SIMD" - "<su>xtl\t%0.<Vwtype>, %1.<Vhalftype>" - [(set_attr "type" "neon_shift_imm_long")] -) - (define_insn_and_split "aarch64_simd_vec_unpack<su>_hi_<mode>" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") (ANY_EXTEND:<VWIDE> (vec_select:<VHALF> @@ -1952,14 +1941,11 @@ ) (define_expand "vec_unpack<su>_lo_<mode>" - [(match_operand:<VWIDE> 0 "register_operand") - (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand"))] + [(set (match_operand:<VWIDE> 0 "register_operand") + (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand")))] "TARGET_SIMD" { - rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false); - emit_insn (gen_aarch64_simd_vec_unpack<su>_lo_<mode> (operands[0], - operands[1], p)); - DONE; + operands[1] = lowpart_subreg (<VHALF>mode, operands[1], <MODE>mode); } ) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 6b106a7..469eb93 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -23188,7 +23188,8 @@ aarch64_gen_shareable_zero (machine_mode mode) to split without that restriction and instead recombine shared zeros if they turn out not to be worthwhile. This would allow splits in single-block functions and would also cope more naturally with - rematerialization. */ + rematerialization. The downside of not doing this is that we lose the + optimizations for vector epilogues as well. */ bool aarch64_split_simd_shift_p (rtx_insn *insn) |