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| author | Vineet Gupta <vineetg@rivosinc.com> | 2022-03-01 03:45:19 -0800 |
|---|---|---|
| committer | Vineet Gupta <vineetg@rivosinc.com> | 2024-05-03 09:33:02 -0700 |
| commit | 467ca4a195e26dba77e7f62cc1a3d45a4e541c72 (patch) | |
| tree | 7269b02e8893afaa739c004f96eb630a44b5a56e /gcc | |
| parent | 301b95494098024317c2f4603f759fadc8a868ca (diff) | |
| download | gcc-467ca4a195e26dba77e7f62cc1a3d45a4e541c72.zip gcc-467ca4a195e26dba77e7f62cc1a3d45a4e541c72.tar.gz gcc-467ca4a195e26dba77e7f62cc1a3d45a4e541c72.tar.bz2 | |
RISC-V: miscll comment fixes [NFC]
gcc/ChangeLog:
* config/riscv/riscv.cc: Comment updates.
* config/riscv/riscv.h: Ditto.
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv.cc | 6 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.h | 2 |
2 files changed, 5 insertions, 3 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 8ed9df8..44945d4 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1258,7 +1258,9 @@ riscv_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x) return riscv_const_insns (x) > 0; } -/* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ +/* Implement TARGET_CANNOT_FORCE_CONST_MEM. + Return true if X cannot (or should not) be spilled to the + constant pool. */ static bool riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) @@ -8624,7 +8626,7 @@ riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2) && GET_MODE_CLASS (mode2) == MODE_FLOAT)); } -/* Implement CLASS_MAX_NREGS. */ +/* Implement TARGET_CLASS_MAX_NREGS. */ static unsigned char riscv_class_max_nregs (reg_class_t rclass, machine_mode mode) diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 7797e67..58d0b09 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -315,7 +315,7 @@ ASM_MISA_SPEC - FRAME_POINTER_REGNUM - 1 vl register - 1 vtype register - - 30 unused registers for future expansion + - 28 unused registers for future expansion - 32 vector registers */ #define FIRST_PSEUDO_REGISTER 128 |