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| author | Christophe Lyon <christophe.lyon@linaro.org> | 2021-03-28 18:59:06 +0000 |
|---|---|---|
| committer | Christophe Lyon <christophe.lyon@linaro.org> | 2021-03-28 19:01:24 +0000 |
| commit | 46720db72cadfb85501e102d94e06683300a2327 (patch) | |
| tree | 7d0a0604d1e818a1d39a27b62a95fc91d54f775d /gcc | |
| parent | 297363774e6a5dca2f46a85ab086f1d9e59431ac (diff) | |
| download | gcc-46720db72cadfb85501e102d94e06683300a2327.zip gcc-46720db72cadfb85501e102d94e06683300a2327.tar.gz gcc-46720db72cadfb85501e102d94e06683300a2327.tar.bz2 | |
testsuite/arm: Improve scan-assembler in pr96770.c
I'm seeing random scan-assembler-times failures in pr96770.c when LTO is used.
I suspect this is because the \\+4 string matches the LTO sections, sometimes.
This small patch avoids the issue, by matching arr\\+4 instead of \\+4.
2021-03-28 Christophe Lyon <christophe.lyon@linaro.org>
gcc/testsuite/
PR target/96770
* gcc.target/arm/pure-code/pr96770.c: Improve scan-assembler-times.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/pure-code/pr96770.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/gcc/testsuite/gcc.target/arm/pure-code/pr96770.c b/gcc/testsuite/gcc.target/arm/pure-code/pr96770.c index a43d71f..ae1bd10 100644 --- a/gcc/testsuite/gcc.target/arm/pure-code/pr96770.c +++ b/gcc/testsuite/gcc.target/arm/pure-code/pr96770.c @@ -5,17 +5,17 @@ int arr[1000]; int *f4 (void) { return &arr[1]; } /* For cortex-m0 (thumb-1/v6m), we generate 4 movs with upper/lower:#arr+4. */ -/* { dg-final { scan-assembler-times "\\+4" 4 { target { { ! arm_thumb1_movt_ok } && { ! arm_thumb2_ok } } } } } */ +/* { dg-final { scan-assembler-times "arr\\+4" 4 { target { { ! arm_thumb1_movt_ok } && { ! arm_thumb2_ok } } } } } */ /* For cortex-m with movt/movw (thumb-1/v8m.base or thumb-2), we generate a movt/movw pair with upper/lower:#arr+4. */ -/* { dg-final { scan-assembler-times "\\+4" 2 { target { arm_thumb1_movt_ok || arm_thumb2_ok } } } } */ +/* { dg-final { scan-assembler-times "arr\\+4" 2 { target { arm_thumb1_movt_ok || arm_thumb2_ok } } } } */ int *f5 (void) { return &arr[80]; } /* For cortex-m0 (thumb-1/v6m), we generate 1 ldr from rodata pointer to arr+320. */ -/* { dg-final { scan-assembler-times "\\+320" 1 { target { { ! arm_thumb1_movt_ok } && { ! arm_thumb2_ok } } } } } */ +/* { dg-final { scan-assembler-times "arr\\+320" 1 { target { { ! arm_thumb1_movt_ok } && { ! arm_thumb2_ok } } } } } */ /* For cortex-m with movt/movw (thumb-1/v8m.base or thumb-2), we generate a movt/movw pair with upper/lower:arr+320. */ -/* { dg-final { scan-assembler-times "\\+320" 2 { target { arm_thumb1_movt_ok || arm_thumb2_ok } } } } */ +/* { dg-final { scan-assembler-times "arr\\+320" 2 { target { arm_thumb1_movt_ok || arm_thumb2_ok } } } } */ |