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| author | Tamar Christina <tamar.christina@arm.com> | 2024-09-20 17:03:54 +0100 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2024-09-20 17:03:54 +0100 |
| commit | 33cb400b2e7266e65030869254366217e51494aa (patch) | |
| tree | 87dc0c85eae9b600c0c772daeed153ca98466689 /gcc | |
| parent | 0189ab205aa86b8e67ae982294f0fe58aa9c4774 (diff) | |
| download | gcc-33cb400b2e7266e65030869254366217e51494aa.zip gcc-33cb400b2e7266e65030869254366217e51494aa.tar.gz gcc-33cb400b2e7266e65030869254366217e51494aa.tar.bz2 | |
AArch64: Define VECTOR_STORE_FLAG_VALUE.
This defines VECTOR_STORE_FLAG_VALUE to CONST1_RTX for AArch64
so we simplify vector comparisons in AArch64.
With this enabled
res:
movi v0.4s, 0
cmeq v0.4s, v0.4s, v0.4s
ret
is simplified to:
res:
mvni v0.4s, 0
ret
gcc/ChangeLog:
* config/aarch64/aarch64.h (VECTOR_STORE_FLAG_VALUE): New.
gcc/testsuite/ChangeLog:
* gcc.dg/rtl/aarch64/vector-eq.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64.h | 10 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/rtl/aarch64/vector-eq.c | 29 |
2 files changed, 39 insertions, 0 deletions
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 2dfb999..a99e7bb 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -156,6 +156,16 @@ #define PCC_BITFIELD_TYPE_MATTERS 1 +/* Use the same RTL truth representation for vector elements as we do + for scalars. This maintains the property that a comparison like + eq:V4SI is a composition of 4 individual eq:SIs, just like plus:V4SI + is a composition of 4 individual plus:SIs. + + This means that Advanced SIMD comparisons are represented in RTL as + (neg (op ...)). */ + +#define VECTOR_STORE_FLAG_VALUE(MODE) CONST1_RTX (GET_MODE_INNER (MODE)) + #ifndef USED_FOR_TARGET /* Define an enum of all features (ISA modes, architectures and extensions). diff --git a/gcc/testsuite/gcc.dg/rtl/aarch64/vector-eq.c b/gcc/testsuite/gcc.dg/rtl/aarch64/vector-eq.c new file mode 100644 index 0000000..8e0d777 --- /dev/null +++ b/gcc/testsuite/gcc.dg/rtl/aarch64/vector-eq.c @@ -0,0 +1,29 @@ +/* { dg-do compile { target aarch64-*-* } } */ +/* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +/* +** foo: +** mvni v0.4s, 0 +** ret +*/ +__Uint32x4_t __RTL (startwith ("vregs")) foo (void) +{ +(function "foo" + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 1 [bb 2] NOTE_INSN_BASIC_BLOCK) + (cnote 2 NOTE_INSN_FUNCTION_BEG) + (cinsn 3 (set (reg:V4SI <0>) (const_vector:V4SI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)]))) + (cinsn 4 (set (reg:V4SI <1>) (reg:V4SI <0>))) + (cinsn 5 (set (reg:V4SI <2>) + (neg:V4SI (eq:V4SI (reg:V4SI <0>) (reg:V4SI <1>))))) + (cinsn 6 (set (reg:V4SI v0) (reg:V4SI <2>))) + (edge-to exit (flags "FALLTHRU")) + ) + ) + (crtl (return_rtx (reg/i:V4SI v0))) +) +} + |