diff options
| author | Torbjörn SVENSSON <torbjorn.svensson@foss.st.com> | 2022-09-23 20:38:45 +0200 |
|---|---|---|
| committer | Torbjörn SVENSSON <torbjorn.svensson@foss.st.com> | 2022-09-25 09:30:32 +0200 |
| commit | 323c38c915f34883439e9e53b9eac5fe07cb8378 (patch) | |
| tree | 500d421bf02f0d684d36c8a77fe3889fc2fd6969 /gcc | |
| parent | 28a61ecdc176edca4bf4affb4c8ac7b9b9a72b06 (diff) | |
| download | gcc-323c38c915f34883439e9e53b9eac5fe07cb8378.zip gcc-323c38c915f34883439e9e53b9eac5fe07cb8378.tar.gz gcc-323c38c915f34883439e9e53b9eac5fe07cb8378.tar.bz2 | |
Fix typo in chapter level for RISC-V attributes
The "RISC-V specific attributes" section should be at the same level
as "PowerPC-specific attributes".
gcc/ChangeLog:
* doc/sourcebuild.texi: Fix chapter level.
Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/doc/sourcebuild.texi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 760ff95..52357cc 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2447,7 +2447,7 @@ PowerPC target pre-defines macro _ARCH_PWR9 which means the @code{-mcpu} setting is Power9 or later. @end table -@subsection RISC-V specific attributes +@subsubsection RISC-V specific attributes @table @code |