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| author | Andrea Corallo <andrea.corallo@arm.com> | 2021-01-15 15:34:19 +0100 |
|---|---|---|
| committer | Andrea Corallo <andrea.corallo@arm.com> | 2021-01-21 14:35:19 +0100 |
| commit | 0568f801effcea6f4e066c40bc346513d6b946c5 (patch) | |
| tree | 89d050bb629a8f729e2db7c5eb96ab7f232a22b5 /gcc | |
| parent | 9be0a89c95cc30089786faa26b89e8d7444c879e (diff) | |
| download | gcc-0568f801effcea6f4e066c40bc346513d6b946c5.zip gcc-0568f801effcea6f4e066c40bc346513d6b946c5.tar.gz gcc-0568f801effcea6f4e066c40bc346513d6b946c5.tar.bz2 | |
arm: [testuiste] Fix ivopts.c target test [PR96372]
gcc/
2021-01-15 Andrea Corallo <andrea.corallo@arm.com>
PR target/96372
* doc/sourcebuild.texi (arm_thumb2_no_arm_v8_1_lob): Document.
gcc/testsuite/
2021-01-15 Andrea Corallo <andrea.corallo@arm.com>
PR target/96372
* lib/target-supports.exp
(check_effective_target_arm_thumb2_no_arm_v8_1_lob): Define proc.
* gcc.target/arm/ivopts.c: Use target
'arm_thumb2_no_arm_v8_1_lob'.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/doc/sourcebuild.texi | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/ivopts.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 15 |
3 files changed, 20 insertions, 2 deletions
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index b9cbe21..cbb7a5b 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2058,6 +2058,11 @@ ARM Target supports executing the Armv8.1-M Mainline Low Overhead Loop instructions @code{DLS} and @code{LE}. Some multilibs may be incompatible with these options. +@item arm_thumb2_no_arm_v8_1_lob +ARM target where Thumb-2 is used without options but does not support +executing the Armv8.1-M Mainline Low Overhead Loop instructions +@code{DLS} and @code{LE}. + @item arm_thumb2_ok_no_arm_v8_1_lob ARM target generates Thumb-2 code for @code{-mthumb} but does not support executing the Armv8.1-M Mainline Low Overhead Loop diff --git a/gcc/testsuite/gcc.target/arm/ivopts.c b/gcc/testsuite/gcc.target/arm/ivopts.c index 2733e66..d7d72a5 100644 --- a/gcc/testsuite/gcc.target/arm/ivopts.c +++ b/gcc/testsuite/gcc.target/arm/ivopts.c @@ -11,6 +11,6 @@ tr5 (short array[], int n) } /* { dg-final { scan-tree-dump-times "PHI <" 1 "ivopts"} } */ -/* { dg-final { object-size text <= 20 { target { arm_thumb2_ok_no_arm_v8_1_lob } } } } */ +/* { dg-final { object-size text <= 20 { target { arm_thumb2_no_arm_v8_1_lob } } } } */ /* { dg-final { object-size text <= 32 { target { arm_nothumb && { ! arm_iwmmxt_ok } } } } } */ /* { dg-final { object-size text <= 36 { target { arm_nothumb && arm_iwmmxt_ok } } } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 47d4c45..0d351c8 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -10658,7 +10658,20 @@ proc check_effective_target_arm_v8_1_lob_ok { } { } } -# Return 1 is this is an ARM target where -mthumb causes Thumb-2 to be +# Return 1 if this is an ARM target where Thumb-2 is used without +# options added by the test and the target does not support executing +# the Armv8.1-M Mainline Low Overhead Loop, 0 otherwise. The test is +# valid for ARM. + +proc check_effective_target_arm_thumb2_no_arm_v8_1_lob { } { + if { [check_effective_target_arm_thumb2] + && ![check_effective_target_arm_v8_1_lob_ok] } { + return 1 + } + return 0 +} + +# Return 1 if this is an ARM target where -mthumb causes Thumb-2 to be # used and the target does not support executing the Armv8.1-M # Mainline Low Overhead Loop, 0 otherwise. The test is valid for ARM. |