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| author | Sheldon Lobo <sheldon.lobo@oracle.com> | 2017-05-18 09:34:26 +0000 |
|---|---|---|
| committer | Sheldon Lobo <smlobo@gcc.gnu.org> | 2017-05-18 09:34:26 +0000 |
| commit | 00a84d0eddec8e671f48e209fffac7c97e6bc4bf (patch) | |
| tree | 3073cf46a77e5e964b3e0c4db99086e8a4fe43b8 /gcc | |
| parent | 243c288370fe51ba55c3a9ee61eb2a1a62cb1279 (diff) | |
| download | gcc-00a84d0eddec8e671f48e209fffac7c97e6bc4bf.zip gcc-00a84d0eddec8e671f48e209fffac7c97e6bc4bf.tar.gz gcc-00a84d0eddec8e671f48e209fffac7c97e6bc4bf.tar.bz2 | |
Minor SPARC T4 and M7 fixes and additions.
* config/sparc/sparc.c (sparc_option_override): Set function
alignment for -mcpu=niagara7 to 64 to match the I$ line.
* config/sparc/sparc.h (BRANCH_COST): Set the SPARC M7 branch
latency to 1.
* config/sparc/sparc.h (BRANCH_COST): Set the SPARC T4 branch
latency to 2.
* config/sparc/sol2.h: Fix a ASM_CPU32_DEFAULT_SPEC typo.
* gcc.target/sparc/niagara7-align.c: New test.
From-SVN: r248184
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/sparc/sol2.h | 2 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.c | 13 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.h | 11 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/sparc/niagara7-align.c | 4 |
6 files changed, 36 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f839cb0..a9978bc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2017-05-18 Sheldon Lobo <sheldon.lobo@oracle.com> + + * config/sparc/sparc.c (sparc_option_override): Set function + alignment for -mcpu=niagara7 to 64 to match the I$ line. + * config/sparc/sparc.h (BRANCH_COST): Set the SPARC M7 branch + latency to 1. + * config/sparc/sparc.h (BRANCH_COST): Set the SPARC T4 branch + latency to 2. + * config/sparc/sol2.h: Fix a ASM_CPU32_DEFAULT_SPEC typo. + 2017-05-18 Marek Polacek <polacek@redhat.com> PR sanitizer/80797 diff --git a/gcc/config/sparc/sol2.h b/gcc/config/sparc/sol2.h index db24ca3..8a50bfe 100644 --- a/gcc/config/sparc/sol2.h +++ b/gcc/config/sparc/sol2.h @@ -169,7 +169,7 @@ along with GCC; see the file COPYING3. If not see #undef CPP_CPU64_DEFAULT_SPEC #define CPP_CPU64_DEFAULT_SPEC "" #undef ASM_CPU32_DEFAULT_SPEC -#define ASM_CPU32_DEFAUILT_SPEC AS_SPARC32_FLAG AS_NIAGARA7_FLAG +#define ASM_CPU32_DEFAULT_SPEC AS_SPARC32_FLAG AS_NIAGARA7_FLAG #undef ASM_CPU64_DEFAULT_SPEC #define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG AS_NIAGARA7_FLAG #endif diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 8277496..6dfb269 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -1528,15 +1528,18 @@ sparc_option_override (void) target_flags |= MASK_LRA; /* Supply a default value for align_functions. */ - if (align_functions == 0 - && (sparc_cpu == PROCESSOR_ULTRASPARC + if (align_functions == 0) + { + if (sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_ULTRASPARC3 || sparc_cpu == PROCESSOR_NIAGARA || sparc_cpu == PROCESSOR_NIAGARA2 || sparc_cpu == PROCESSOR_NIAGARA3 - || sparc_cpu == PROCESSOR_NIAGARA4 - || sparc_cpu == PROCESSOR_NIAGARA7)) - align_functions = 32; + || sparc_cpu == PROCESSOR_NIAGARA4) + align_functions = 32; + else if (sparc_cpu == PROCESSOR_NIAGARA7) + align_functions = 64; + } /* Validate PCC_STRUCT_RETURN. */ if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN) diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 590a5f4..686a3d5 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -1566,7 +1566,10 @@ do { \ and annulled branches insert 4 bubbles. On Niagara-2 and Niagara-3, a not-taken branch costs 1 cycle whereas - a taken branch costs 6 cycles. */ + a taken branch costs 6 cycles. + + The T4 Supplement specifies the branch latency at 2 cycles. + The M7 Supplement specifies the branch latency at 1 cycle. */ #define BRANCH_COST(speed_p, predictable_p) \ ((sparc_cpu == PROCESSOR_V9 \ @@ -1579,7 +1582,11 @@ do { \ : ((sparc_cpu == PROCESSOR_NIAGARA2 \ || sparc_cpu == PROCESSOR_NIAGARA3) \ ? 5 \ - : 3)))) + : (sparc_cpu == PROCESSOR_NIAGARA4 \ + ? 2 \ + : (sparc_cpu == PROCESSOR_NIAGARA7 \ + ? 1 \ + : 3)))))) /* Control the assembler format that we output. */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d5ea15c..fca9165 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-05-18 Sheldon Lobo <sheldon.lobo@oracle.com> + + * gcc.target/sparc/niagara7-align.c: New test. + 2017-05-18 Marek Polacek <polacek@redhat.com> PR sanitizer/80797 diff --git a/gcc/testsuite/gcc.target/sparc/niagara7-align.c b/gcc/testsuite/gcc.target/sparc/niagara7-align.c new file mode 100644 index 0000000..a46aac1 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/niagara7-align.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-falign-functions -mcpu=niagara7" } */ +/* { dg-final { scan-assembler "\.align 64" } } */ +void foo(void) {} |