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| author | Richard Earnshaw <rearnsha@arm.com> | 2021-09-03 16:53:13 +0100 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@arm.com> | 2021-09-13 11:26:48 +0100 |
| commit | f0cfd070b68772eaaa19a3b711fbd9e85b244240 (patch) | |
| tree | 05f3449d545f645847aa73b935be4b66dba4d68d /gcc | |
| parent | 408e8b906632f215f6652b8851bba612cde07c25 (diff) | |
| download | gcc-f0cfd070b68772eaaa19a3b711fbd9e85b244240.zip gcc-f0cfd070b68772eaaa19a3b711fbd9e85b244240.tar.gz gcc-f0cfd070b68772eaaa19a3b711fbd9e85b244240.tar.bz2 | |
arm: expand handling of movmisalign for DImode [PR102125]
DImode is currently handled only for machines with vector modes
enabled, but this is unduly restrictive and is generally better done
in core registers.
gcc/ChangeLog:
PR target/102125
* config/arm/arm.md (movmisaligndi): New define_expand.
* config/arm/vec-common.md (movmisalign<mode>): Iterate over VDQ mode.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/arm/arm.md | 16 | ||||
| -rw-r--r-- | gcc/config/arm/vec-common.md | 4 |
2 files changed, 18 insertions, 2 deletions
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 5d3f21b..4adc976 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12617,6 +12617,22 @@ }" ) +;; movmisalign for DImode +(define_expand "movmisaligndi" + [(match_operand:DI 0 "general_operand") + (match_operand:DI 1 "general_operand")] + "unaligned_access" +{ + rtx lo_op0 = gen_lowpart (SImode, operands[0]); + rtx lo_op1 = gen_lowpart (SImode, operands[1]); + rtx hi_op0 = gen_highpart_mode (SImode, DImode, operands[0]); + rtx hi_op1 = gen_highpart_mode (SImode, DImode, operands[1]); + + emit_insn (gen_movmisalignsi (lo_op0, lo_op1)); + emit_insn (gen_movmisalignsi (hi_op0, hi_op1)); + DONE; +}) + ;; movmisalign patterns for HImode and SImode. (define_expand "movmisalign<mode>" [(match_operand:HSI 0 "general_operand") diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 68de4f0..e71d9b3 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -281,8 +281,8 @@ }) (define_expand "movmisalign<mode>" - [(set (match_operand:VDQX 0 "neon_perm_struct_or_reg_operand") - (unspec:VDQX [(match_operand:VDQX 1 "neon_perm_struct_or_reg_operand")] + [(set (match_operand:VDQ 0 "neon_perm_struct_or_reg_operand") + (unspec:VDQ [(match_operand:VDQ 1 "neon_perm_struct_or_reg_operand")] UNSPEC_MISALIGNED_ACCESS))] "ARM_HAVE_<MODE>_LDST && !BYTES_BIG_ENDIAN && unaligned_access && !TARGET_REALLY_IWMMXT" |