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authorMichael Meissner <meissner@linux.vnet.ibm.com>2017-11-14 23:04:27 +0000
committerMichael Meissner <meissner@gcc.gnu.org>2017-11-14 23:04:27 +0000
commitec0c1fab90919d616141aefaac09cee0803a909b (patch)
tree4c0a5ba28c87d09447ad70843e51ef0e8178f2bb /gcc
parentcdb4b7aa2f7a6e3b437c0d99e23f8e402b8eeb7d (diff)
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rs6000.md (bswapdi2): On 32-bit ISA 3.0, don't generate the XXBRD instruction.
2017-11-14 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000.md (bswapdi2): On 32-bit ISA 3.0, don't generate the XXBRD instruction. From-SVN: r254742
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog3
-rw-r--r--gcc/config/rs6000/rs6000.md6
2 files changed, 3 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0acc100..15f391f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
2017-11-14 Michael Meissner <meissner@linux.vnet.ibm.com>
+ * config/rs6000/rs6000.md (bswapdi2): On 32-bit ISA 3.0, don't
+ generate the XXBRD instruction.
+
* config/rs6000/rs6000-c.c (is_float128_p): New helper function.
(rs6000_builtin_type_compatible): Treat _Float128 and long double
as being compatible if -mabi=ieeelongdouble.
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 9b0f872..276ad8a 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -2520,12 +2520,6 @@
DONE;
}
- if (TARGET_P9_VECTOR && !MEM_P (src) && !MEM_P (dest))
- {
- emit_insn (gen_bswapdi2_xxbrd (dest, src));
- DONE;
- }
-
if (!TARGET_POWERPC64)
{
/* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode