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| author | Richard Earnshaw <rearnsha@arm.com> | 2004-06-23 11:39:32 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2004-06-23 11:39:32 +0000 |
| commit | e1d2bd1e44971a4becd718272277361b4f64fcad (patch) | |
| tree | d40bc79e1b8cf1a29e8de01cb7e51a378f3533ae /gcc | |
| parent | 97358092a486fda247a0e3bcd72cb2a1ab6f45d0 (diff) | |
| download | gcc-e1d2bd1e44971a4becd718272277361b4f64fcad.zip gcc-e1d2bd1e44971a4becd718272277361b4f64fcad.tar.gz gcc-e1d2bd1e44971a4becd718272277361b4f64fcad.tar.bz2 | |
re PR target/15948 (THUMB: ICE with non-commutative cbranch)
* PR target/15948
* arm.md (bicsi3_cbranch): Add alternative to handle tying operands
one and two.
From-SVN: r83549
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 12 |
2 files changed, 13 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 534cfae..db45e7e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2004-06-23 Richard Earnshaw <rearnsha@arm.com> + * PR target/15948 + * arm.md (bicsi3_cbranch): Add alternative to handle tying operands + one and two. + +2004-06-23 Richard Earnshaw <rearnsha@arm.com> + PR target/15927 * arm.h (THUMB_SECONDARY_OUTPUT_RELOAD_CLASS): Don't need a secondary reload if CLASS is BASE_REGS. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 82f1701..fb13fe0 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -6167,22 +6167,24 @@ [(set (pc) (if_then_else (match_operator 5 "equality_operator" - [(and:SI (not:SI (match_operand:SI 3 "s_register_operand" "l,l,l,l")) - (match_operand:SI 2 "s_register_operand" "0,1,1,1")) + [(and:SI (not:SI (match_operand:SI 3 "s_register_operand" "l,l,l,l,l")) + (match_operand:SI 2 "s_register_operand" "0,1,1,1,1")) (const_int 0)]) (label_ref (match_operand 4 "" "")) (pc))) - (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") + (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=!l,l,*?h,*?m,*?m") (and:SI (not:SI (match_dup 3)) (match_dup 2))) - (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] + (clobber (match_scratch:SI 1 "=X,l,l,&l,&l"))] "TARGET_THUMB" "* { if (which_alternative == 0) output_asm_insn (\"bic\\t%0, %3\", operands); - else if (which_alternative == 1) + else if (which_alternative <= 2) { output_asm_insn (\"bic\\t%1, %3\", operands); + /* It's ok if OP0 is a lo-reg, even though the mov will set the + conditions again, since we're only testing for equality. */ output_asm_insn (\"mov\\t%0, %1\", operands); } else |