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| author | Richard Henderson <rth@redhat.com> | 2001-07-18 14:34:15 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 2001-07-18 14:34:15 -0700 |
| commit | d989f648fa20fdb23338fe92c1e14c071fd36a6a (patch) | |
| tree | 68a2c6b74e7745337eb652ff18ec1400a42fe871 /gcc | |
| parent | 31831acf291f3146c15a7cf3568188527a1cf425 (diff) | |
| download | gcc-d989f648fa20fdb23338fe92c1e14c071fd36a6a.zip gcc-d989f648fa20fdb23338fe92c1e14c071fd36a6a.tar.gz gcc-d989f648fa20fdb23338fe92c1e14c071fd36a6a.tar.bz2 | |
md.texi (reload_in/out): Document restrictions in predicates and constraints for these patterns.
* doc/md.texi (reload_in/out): Document restrictions in predicates
and constraints for these patterns. Document empty string matching
ALL_REGS.
From-SVN: r44134
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/doc/md.texi | 11 |
2 files changed, 17 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 216bba6..dfe38ac 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2001-07-18 Richard Henderson <rth@redhat.com> + + * doc/md.texi (reload_in/out): Document restrictions in predicates + and constraints for these patterns. Document empty string matching + ALL_REGS. + 2001-07-18 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE> * defaults.h (ASM_OUTPUT_WEAK_ALIAS): Check for ASM_WEAKEN_LABEL. diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index f1073aa..0b680cd 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -2076,6 +2076,17 @@ move between operand 0 and operand 1. Operand 2 describes the scratch register. See the discussion of the @code{SECONDARY_RELOAD_CLASS} macro in @pxref{Register Classes}. +There are special restrictions on the form of the @code{match_operand}s +used in these patterns. First, only the predicate for the reload +operand is examined, i.e. @code{reload_in} examines operand 1, but not +the predicates for operand 0 or 2. Second, there may only be one +alternative in the constraints. Third, only a single register class +letter may be used for the constraint; subsequent constraint letters +are ignored. As a special exception, an empty constraint string +matches the @code{ALL_REGS} register class. This may relieve ports +of the burden of defining an @code{ALL_REGS} constraint letter just +for these patterns. + @cindex @code{movstrict@var{m}} instruction pattern @item @samp{movstrict@var{m}} Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg} |