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authorDwarakanath Rajagopal <dwarak.rajagopal@amd.com>2007-05-01 19:53:40 +0000
committerDwarakanath Rajagopal <dwarak@gcc.gnu.org>2007-05-01 19:53:40 +0000
commitd8f52b02324d61f48bbdf5ebe995038d22fb1b66 (patch)
tree9165fe6e8da65fdcf73f90ffbf48c92d00928d55 /gcc
parent9369ed9561ea7a5f19486a9a1fe32d7ae3b8c500 (diff)
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invoke.texi: Fix typo, 'AMD Family 10h core' instead of 'AMD Family 10 core'.
2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * doc/invoke.texi: Fix typo, 'AMD Family 10h core' instead of 'AMD Family 10 core'. From-SVN: r124341
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/doc/invoke.texi2
2 files changed, 6 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3ee41a5..c3e3a23 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,10 @@
2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
+ * doc/invoke.texi: Fix typo, 'AMD Family 10h core' instead of
+ 'AMD Family 10 core'.
+
+2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
+
* config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3
and athlon64-sse3 as improved versions of k8, opteron and athlon64
with SSE3 instruction set support.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 9252a46..07bf9e9 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -9894,7 +9894,7 @@ MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.)
@item k8-sse3, opteron-sse3, athlon64-sse3
Improved versions of k8, opteron and athlon64 with SSE3 instruction set support.
@item amdfam10, barcelona
-AMD Family 10 core based CPUs with x86-64 instruction set support. (This
+AMD Family 10h core based CPUs with x86-64 instruction set support. (This
supersets MMX, SSE, SSE2, SSE3, SSE4A, 3dNOW!, enhanced 3dNOW!, ABM and 64-bit
instruction set extensions.)
@item winchip-c6