i386.md (SWIM): New mode iterator.

	* config/i386/i386.md (SWIM): New mode iterator.
	(mov<mode>cc): Macroize expander from mov{qi,hi,si,di}cc patterns
	using SWIM mode iterator.
	(x86_mov<mode>cc_0_m1): Macroize insn from x86_mov{si,di}cc_0_m1
	patterns using SWI48 mode iterator.
	(*x86_mov<mode>cc_0_m1_se):  Macroize insn from
	*x86_mov{si,di}cc_0_m1_se patterns using SWI48 mode iterator.
	(*x86_mov<mode>cc_0_m1_neg): New insn pattern.
	(*mov<mode>cc_noc): Macroize insn from *mov{hi,si,di}cc_noc
	patterns using SWI248 mode iterator.
	* config/i386/i386.c (ix86_expand_int_movcc): Update the call to
	gen_x86_movdicc_0_m1_rex64 for renamed function

From-SVN: r152650

3 files changed, 62 insertions, 115 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4ef144e..c7f8749 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2009-10-12  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (SWIM): New mode iterator.
+	(mov<mode>cc): Macroize expander from mov{qi,hi,si,di}cc patterns
+	using SWIM mode iterator.
+	(x86_mov<mode>cc_0_m1): Macroize insn from x86_mov{si,di}cc_0_m1
+	patterns using SWI48 mode iterator.
+	(*x86_mov<mode>cc_0_m1_se):  Macroize insn from
+	*x86_mov{si,di}cc_0_m1_se patterns using SWI48 mode iterator.
+	(*x86_mov<mode>cc_0_m1_neg): New insn pattern.
+	(*mov<mode>cc_noc): Macroize insn from *mov{hi,si,di}cc_noc
+	patterns using SWI248 mode iterator.
+	* config/i386/i386.c (ix86_expand_int_movcc): Update the call to
+	gen_x86_movdicc_0_m1_rex64 for renamed function
+
 2009-10-11  Jose Ruiz  <ruiz@adacore.com>
             Eric Botcazou  <ebotcazou@adacore.com>
 
@@ -569,7 +584,7 @@
 	patterns using plusminus code iterator.
 	(<plusminus_insn><mode>3): Macroize expander from add<mode>3 and
 	sub<mode>3 patterns using plusminus code iterator.
-	* config/i386/i386.c (override_options): Update call to
+	* config/i386/i386.c (override_options): Update the call to
 	gen_subdi_carry_rex64 for renamed function.
 	(ix86_expand_int_addcc): Update calls to gen_subdi3_carry_rex64
 	and gen_adddi3_carry_rex64 for renamed functions.  Use indirect
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 2a1ed6d..b5bb6a0 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -15247,9 +15247,10 @@ ix86_expand_int_movcc (rtx operands[])
 		tmp = gen_reg_rtx (mode);
 
 	      if (mode == DImode)
-		emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
+		emit_insn (gen_x86_movdicc_0_m1 (tmp, compare_op));
 	      else
-		emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
+		emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp),
+						 compare_op));
 	    }
 	  else
 	    {
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 89f075e..63de5b9 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -731,6 +731,11 @@
 			     (HI "TARGET_HIMODE_MATH")
 			     SI DI (TI "TARGET_64BIT")])
 
+;; Math-dependant single word integer modes.
+(define_mode_iterator SWIM [(QI "TARGET_QIMODE_MATH")
+			    (HI "TARGET_HIMODE_MATH")
+			    SI (DI "TARGET_64BIT")])
+
 ;; Math-dependant single word integer modes without QImode.
 (define_mode_iterator SWIM248 [(HI "TARGET_HIMODE_MATH")
 		      	       SI (DI "TARGET_64BIT")])
@@ -19468,22 +19473,26 @@
 
 ;; Conditional move instructions.
 
-(define_expand "movdicc"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(if_then_else:DI (match_operand 1 "comparison_operator" "")
-			 (match_operand:DI 2 "general_operand" "")
-			 (match_operand:DI 3 "general_operand" "")))]
-  "TARGET_64BIT"
+(define_expand "mov<mode>cc"
+  [(set (match_operand:SWIM 0 "register_operand" "")
+	(if_then_else:SWIM (match_operand 1 "comparison_operator" "")
+			   (match_operand:SWIM 2 "general_operand" "")
+			   (match_operand:SWIM 3 "general_operand" "")))]
+  ""
   "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
 
-(define_insn "x86_movdicc_0_m1_rex64"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "")
+;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
+;; the register first winds up with `sbbl $0,reg', which is also weird.
+;; So just document what we're doing explicitly.
+
+(define_insn "x86_mov<mode>cc_0_m1"
+  [(set (match_operand:SWI48 0 "register_operand" "=r")
+	(if_then_else:SWI48 (match_operand 1 "ix86_carry_flag_operator" "")
 	  (const_int -1)
 	  (const_int 0)))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT"
-  "sbb{q}\t%0, %0"
+  ""
+  "sbb{<imodesuffix>}\t%0, %0"
   ; Since we don't have the proper number of operands for an alu insn,
   ; fill in all the blanks.
   [(set_attr "type" "alu")
@@ -19491,134 +19500,56 @@
    (set_attr "pent_pair" "pu")
    (set_attr "memory" "none")
    (set_attr "imm_disp" "false")
-   (set_attr "mode" "DI")
-   (set_attr "length_immediate" "0")])
-
-(define_insn "*x86_movdicc_0_m1_se"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(sign_extract:DI (match_operand 1 "ix86_carry_flag_operator" "")
-			 (const_int 1)
-			 (const_int 0)))
-   (clobber (reg:CC FLAGS_REG))]
-  ""
-  "sbb{q}\t%0, %0"
-  [(set_attr "type" "alu")
-   (set_attr "use_carry" "1")
-   (set_attr "pent_pair" "pu")
-   (set_attr "memory" "none")
-   (set_attr "imm_disp" "false")
-   (set_attr "mode" "DI")
+   (set_attr "mode" "<MODE>")
    (set_attr "length_immediate" "0")])
 
-(define_insn "*movdicc_c_rex64"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(if_then_else:DI (match_operator 1 "ix86_comparison_operator"
-				[(reg FLAGS_REG) (const_int 0)])
-		      (match_operand:DI 2 "nonimmediate_operand" "rm,0")
-		      (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
-  "TARGET_64BIT && TARGET_CMOVE
-   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
-  "@
-   cmov%O2%C1\t{%2, %0|%0, %2}
-   cmov%O2%c1\t{%3, %0|%0, %3}"
-  [(set_attr "type" "icmov")
-   (set_attr "mode" "DI")])
-
-(define_expand "movsicc"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(if_then_else:SI (match_operand 1 "comparison_operator" "")
-			 (match_operand:SI 2 "general_operand" "")
-			 (match_operand:SI 3 "general_operand" "")))]
-  ""
-  "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
-
-;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
-;; the register first winds up with `sbbl $0,reg', which is also weird.
-;; So just document what we're doing explicitly.
-
-(define_insn "x86_movsicc_0_m1"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "")
-	  (const_int -1)
-	  (const_int 0)))
+(define_insn "*x86_mov<mode>cc_0_m1_se"
+  [(set (match_operand:SWI48 0 "register_operand" "=r")
+	(sign_extract:SWI48 (match_operand 1 "ix86_carry_flag_operator" "")
+			    (const_int 1)
+			    (const_int 0)))
    (clobber (reg:CC FLAGS_REG))]
   ""
-  "sbb{l}\t%0, %0"
-  ; Since we don't have the proper number of operands for an alu insn,
-  ; fill in all the blanks.
+  "sbb{<imodesuffix>}\t%0, %0"
   [(set_attr "type" "alu")
    (set_attr "use_carry" "1")
    (set_attr "pent_pair" "pu")
    (set_attr "memory" "none")
    (set_attr "imm_disp" "false")
-   (set_attr "mode" "SI")
+   (set_attr "mode" "<MODE>")
    (set_attr "length_immediate" "0")])
 
-(define_insn "*x86_movsicc_0_m1_se"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extract:SI (match_operand 1 "ix86_carry_flag_operator" "")
-			 (const_int 1)
-			 (const_int 0)))
-   (clobber (reg:CC FLAGS_REG))]
+(define_insn "*x86_mov<mode>cc_0_m1_neg"
+  [(set (match_operand:SWI48 0 "register_operand" "=r")
+	(neg:SWI48 (match_operand 1 "ix86_carry_flag_operator" "")))]
   ""
-  "sbb{l}\t%0, %0"
+  "sbb{<imodesuffix>}\t%0, %0"
   [(set_attr "type" "alu")
    (set_attr "use_carry" "1")
    (set_attr "pent_pair" "pu")
    (set_attr "memory" "none")
    (set_attr "imm_disp" "false")
-   (set_attr "mode" "SI")
+   (set_attr "mode" "<MODE>")
    (set_attr "length_immediate" "0")])
 
-(define_insn "*movsicc_noc"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(if_then_else:SI (match_operator 1 "ix86_comparison_operator"
-				[(reg FLAGS_REG) (const_int 0)])
-		      (match_operand:SI 2 "nonimmediate_operand" "rm,0")
-		      (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
-  "TARGET_CMOVE
-   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
-  "@
-   cmov%O2%C1\t{%2, %0|%0, %2}
-   cmov%O2%c1\t{%3, %0|%0, %3}"
-  [(set_attr "type" "icmov")
-   (set_attr "mode" "SI")])
-
-(define_expand "movhicc"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(if_then_else:HI (match_operand 1 "comparison_operator" "")
-			 (match_operand:HI 2 "general_operand" "")
-			 (match_operand:HI 3 "general_operand" "")))]
-  "TARGET_HIMODE_MATH"
-  "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
-
-(define_insn "*movhicc_noc"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(if_then_else:HI (match_operator 1 "ix86_comparison_operator"
-				[(reg FLAGS_REG) (const_int 0)])
-		      (match_operand:HI 2 "nonimmediate_operand" "rm,0")
-		      (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
-  "TARGET_CMOVE
-   && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+(define_insn "*mov<mode>cc_noc"
+  [(set (match_operand:SWI248 0 "register_operand" "=r,r")
+	(if_then_else:SWI248 (match_operator 1 "ix86_comparison_operator"
+			       [(reg FLAGS_REG) (const_int 0)])
+	  (match_operand:SWI248 2 "nonimmediate_operand" "rm,0")
+	  (match_operand:SWI248 3 "nonimmediate_operand" "0,rm")))]
+  "TARGET_CMOVE && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "@
    cmov%O2%C1\t{%2, %0|%0, %2}
    cmov%O2%c1\t{%3, %0|%0, %3}"
   [(set_attr "type" "icmov")
-   (set_attr "mode" "HI")])
-
-(define_expand "movqicc"
-  [(set (match_operand:QI 0 "register_operand" "")
-	(if_then_else:QI (match_operand 1 "comparison_operator" "")
-			 (match_operand:QI 2 "general_operand" "")
-			 (match_operand:QI 3 "general_operand" "")))]
-  "TARGET_QIMODE_MATH"
-  "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
+   (set_attr "mode" "<MODE>")])
 
 (define_insn_and_split "*movqicc_noc"
   [(set (match_operand:QI 0 "register_operand" "=r,r")
 	(if_then_else:QI (match_operator 1 "ix86_comparison_operator"
-				[(match_operand 4 "flags_reg_operand" "")
-				 (const_int 0)])
+			   [(match_operand 4 "flags_reg_operand" "")
+			    (const_int 0)])
 		      (match_operand:QI 2 "register_operand" "r,0")
 		      (match_operand:QI 3 "register_operand" "0,r")))]
   "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"