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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-05-09 07:43:32 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-05-09 07:43:32 +0100 |
| commit | aebd8471a172706fe645c4fc931b085d4f040b49 (patch) | |
| tree | 47990571f1948b5ddc591c393dfb75b097e19aaa /gcc | |
| parent | ba72a8d85180d0f4dbcea6eb3458ce175ce190b4 (diff) | |
| download | gcc-aebd8471a172706fe645c4fc931b085d4f040b49.zip gcc-aebd8471a172706fe645c4fc931b085d4f040b49.tar.gz gcc-aebd8471a172706fe645c4fc931b085d4f040b49.tar.bz2 | |
aarch64: Fix move-after-intrinsic function-body tests
Some of the SVE ACLE asm tests tried to be agnostic about the
instruction order, but only one of the alternatives was exercised
in practice. This patch fixes latent typos in the other versions.
gcc/testsuite/
* gcc.target/aarch64/sve2/acle/asm/aesd_u8.c: Fix expected register
allocation in the case where a move occurs after the intrinsic
instruction.
* gcc.target/aarch64/sve2/acle/asm/aese_u8.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c: Likewise.
Diffstat (limited to 'gcc')
5 files changed, 7 insertions, 7 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesd_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesd_u8.c index 622f5cf..384b6ff 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesd_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesd_u8.c @@ -28,13 +28,13 @@ TEST_UNIFORM_Z (aesd_u8_tied2, svuint8_t, ** mov z0\.d, z1\.d ** aesd z0\.b, z0\.b, z2\.b ** | -** aesd z1\.b, z0\.b, z2\.b +** aesd z1\.b, z1\.b, z2\.b ** mov z0\.d, z1\.d ** | ** mov z0\.d, z2\.d ** aesd z0\.b, z0\.b, z1\.b ** | -** aesd z2\.b, z0\.b, z1\.b +** aesd z2\.b, z2\.b, z1\.b ** mov z0\.d, z2\.d ** ) ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aese_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aese_u8.c index 6555bbb..6381bce 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aese_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aese_u8.c @@ -28,13 +28,13 @@ TEST_UNIFORM_Z (aese_u8_tied2, svuint8_t, ** mov z0\.d, z1\.d ** aese z0\.b, z0\.b, z2\.b ** | -** aese z1\.b, z0\.b, z2\.b +** aese z1\.b, z1\.b, z2\.b ** mov z0\.d, z1\.d ** | ** mov z0\.d, z2\.d ** aese z0\.b, z0\.b, z1\.b ** | -** aese z2\.b, z0\.b, z1\.b +** aese z2\.b, z2\.b, z1\.b ** mov z0\.d, z2\.d ** ) ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c index 4630595..7625932 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c @@ -19,7 +19,7 @@ TEST_UNIFORM_Z (aesimc_u8_tied1, svuint8_t, ** mov z0\.d, z1\.d ** aesimc z0\.b, z0\.b ** | -** aesimc z1\.b, z0\.b +** aesimc z1\.b, z1\.b ** mov z0\.d, z1\.d ** ) ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c index 6e8acf4..30e83d3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c @@ -19,7 +19,7 @@ TEST_UNIFORM_Z (aesmc_u8_tied1, svuint8_t, ** mov z0\.d, z1\.d ** aesmc z0\.b, z0\.b ** | -** aesmc z1\.b, z0\.b +** aesmc z1\.b, z1\.b ** mov z0\.d, z1\.d ** ) ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c index 0ff5746..cf6a2a9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c @@ -24,7 +24,7 @@ TEST_UNIFORM_Z (sm4e_u32_tied2, svuint32_t, ** mov z0\.d, z1\.d ** sm4e z0\.s, z0\.s, z2\.s ** | -** sm4e z1\.s, z0\.s, z2\.s +** sm4e z1\.s, z1\.s, z2\.s ** mov z0\.d, z1\.d ** ) ** ret |