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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2012-11-20 19:29:02 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2012-11-20 19:29:02 +0000 |
| commit | 96ceaa374efabc4d137c416fcdd62f9f158abbde (patch) | |
| tree | d84bb4db28c514084202f9dac829835f7acd97ed /gcc | |
| parent | 7139194bf9ee6158e94d4ddfb47dcfcdb338eae4 (diff) | |
| download | gcc-96ceaa374efabc4d137c416fcdd62f9f158abbde.zip gcc-96ceaa374efabc4d137c416fcdd62f9f158abbde.tar.gz gcc-96ceaa374efabc4d137c416fcdd62f9f158abbde.tar.bz2 | |
rs6000.md (movdf_hardfloat32): Add a comment explaining the register ordering preferences.
2012-11-20 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.md (movdf_hardfloat32): Add a comment
explaining the register ordering preferences.
From-SVN: r193673
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 8 |
2 files changed, 13 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 09ab535..30a6112 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2012-11-20 Michael Meissner <meissner@linux.vnet.ibm.com> + + * config/rs6000/rs6000.md (movdf_hardfloat32): Add a comment + explaining the register ordering preferences. + 2012-11-20 Aldy Hernandez <aldyh@redhat.com> PR tree-optimization/55350 diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 2568203..7719ec3 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8018,6 +8018,14 @@ ;; Don't have reload use general registers to load a constant. It is ;; less efficient than loading the constant into an FP register, since ;; it will probably be used there. + +;; The move constraints are ordered to prefer floating point registers before +;; general purpose registers to avoid doing a store and a load to get the value +;; into a floating point register when it is needed for a floating point +;; operation. Prefer traditional floating point registers over VSX registers, +;; since the D-form version of the memory instructions does not need a GPR for +;; reloading. + (define_insn "*movdf_hardfloat32" [(set (match_operand:DF 0 "nonimmediate_operand" "=m,d,d,ws,?wa,Z,?Z,ws,?wa,wa,Y,r,!r,!r,!r,!r") (match_operand:DF 1 "input_operand" "d,m,d,Z,Z,ws,wa,ws,wa,j,r,Y,r,G,H,F"))] |