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| author | Andrew Stubbs <ams@codesourcery.com> | 2019-12-19 13:59:05 +0000 |
|---|---|---|
| committer | Andrew Stubbs <ams@gcc.gnu.org> | 2019-12-19 13:59:05 +0000 |
| commit | 77f7566e32f3f5be5d3baf38ea7dad08a107fd00 (patch) | |
| tree | b5667cfe0e35881bc351924c1501624c8cb96ed2 /gcc | |
| parent | 2b91bb48997ec1d695a2f4c0f132958c79f2b145 (diff) | |
| download | gcc-77f7566e32f3f5be5d3baf38ea7dad08a107fd00.zip gcc-77f7566e32f3f5be5d3baf38ea7dad08a107fd00.tar.gz gcc-77f7566e32f3f5be5d3baf38ea7dad08a107fd00.tar.bz2 | |
Implement sub-dword add/sub on amdgcn
2019-12-19 Andrew Stubbs <ams@codesourcery.com>
gcc/
* config/gcn/gcn-valu.md (addv64si3<exec_clobber>): Rename to ...
(add<mode>3<exec_clobber>): ... this, and use VEC_ALL1REG_INT_MODE.
(addv64si3_dup<exec_clobber>): Rename to ...
(add<mode>3_dup<exec_clobber>): ... this, and use VEC_ALL1REG_INT_MODE.
(subv64si3<exec_clobber>): Rename to ...
(sub<mode>3<exec_clobber>): ... this, and use VEC_ALL1REG_INT_MODE.
From-SVN: r279574
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/gcn/gcn-valu.md | 32 |
2 files changed, 25 insertions, 16 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 542bdf6..9126ec1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2019-12-19 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn-valu.md (addv64si3<exec_clobber>): Rename to ... + (add<mode>3<exec_clobber>): ... this, and use VEC_ALL1REG_INT_MODE. + (addv64si3_dup<exec_clobber>): Rename to ... + (add<mode>3_dup<exec_clobber>): ... this, and use VEC_ALL1REG_INT_MODE. + (subv64si3<exec_clobber>): Rename to ... + (sub<mode>3<exec_clobber>): ... this, and use VEC_ALL1REG_INT_MODE. + 2019-12-19 Richard Sandiford <richard.sandiford@arm.com> * config/aarch64/aarch64.c (aarch64_can_change_mode_class): diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index 3b3be8a..00a7604 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -1036,23 +1036,23 @@ ;; }}} ;; {{{ ALU special case: add/sub -(define_insn "addv64si3<exec_clobber>" - [(set (match_operand:V64SI 0 "register_operand" "= v") - (plus:V64SI - (match_operand:V64SI 1 "register_operand" "% v") - (match_operand:V64SI 2 "gcn_alu_operand" "vSvB"))) +(define_insn "add<mode>3<exec_clobber>" + [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "= v") + (plus:VEC_ALL1REG_INT_MODE + (match_operand:VEC_ALL1REG_INT_MODE 1 "register_operand" "% v") + (match_operand:VEC_ALL1REG_INT_MODE 2 "gcn_alu_operand" "vSvB"))) (clobber (reg:DI VCC_REG))] "" "v_add%^_u32\t%0, vcc, %2, %1" [(set_attr "type" "vop2") (set_attr "length" "8")]) -(define_insn "addv64si3_dup<exec_clobber>" - [(set (match_operand:V64SI 0 "register_operand" "= v") - (plus:V64SI - (vec_duplicate:V64SI - (match_operand:SI 2 "gcn_alu_operand" "SvB")) - (match_operand:V64SI 1 "register_operand" " v"))) +(define_insn "add<mode>3_dup<exec_clobber>" + [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "= v") + (plus:VEC_ALL1REG_INT_MODE + (vec_duplicate:VEC_ALL1REG_INT_MODE + (match_operand:<SCALAR_MODE> 2 "gcn_alu_operand" "SvB")) + (match_operand:VEC_ALL1REG_INT_MODE 1 "register_operand" " v"))) (clobber (reg:DI VCC_REG))] "" "v_add%^_u32\t%0, vcc, %2, %1" @@ -1158,11 +1158,11 @@ [(set_attr "type" "vop2,vop3b") (set_attr "length" "4,8")]) -(define_insn "subv64si3<exec_clobber>" - [(set (match_operand:V64SI 0 "register_operand" "= v, v") - (minus:V64SI - (match_operand:V64SI 1 "gcn_alu_operand" "vSvB, v") - (match_operand:V64SI 2 "gcn_alu_operand" " v,vSvB"))) +(define_insn "sub<mode>3<exec_clobber>" + [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "= v, v") + (minus:VEC_ALL1REG_INT_MODE + (match_operand:VEC_ALL1REG_INT_MODE 1 "gcn_alu_operand" "vSvB, v") + (match_operand:VEC_ALL1REG_INT_MODE 2 "gcn_alu_operand" " v,vSvB"))) (clobber (reg:DI VCC_REG))] "" "@ |