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| author | Kito Cheng <kito.cheng@sifive.com> | 2023-03-28 22:21:50 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2023-03-28 22:59:54 +0800 |
| commit | 5a923516ae61ddc6dd863891db13189cbf392411 (patch) | |
| tree | 0ae36b1064983104f17804d8001287ee4612f9b9 /gcc | |
| parent | 97383b4116ea63486eb5bfb0a7140871bed75fb4 (diff) | |
| download | gcc-5a923516ae61ddc6dd863891db13189cbf392411.zip gcc-5a923516ae61ddc6dd863891db13189cbf392411.tar.gz gcc-5a923516ae61ddc6dd863891db13189cbf392411.tar.bz2 | |
RISC-V: Define __riscv_v_intrinsic [PR109312]
RVV intrinsic has defined a macro to identity the version of RVV
intrinsic spec, we missed that before, thanksful we are catch this
before release.
gcc/ChangeLog:
PR target/109312
* config/riscv/riscv-c.cc (riscv_ext_version_value): New.
(riscv_cpu_cpp_builtins): Define __riscv_v_intrinsic and
minor refactor.
gcc/testsuite/ChangeLog:
PR target/109312
* gcc.target/riscv/predef-__riscv_v_intrinsic.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv-c.cc | 18 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c | 11 |
2 files changed, 25 insertions, 4 deletions
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index ff07d31..6ad562d 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -34,6 +34,12 @@ along with GCC; see the file COPYING3. If not see #define builtin_define(TXT) cpp_define (pfile, TXT) +static int +riscv_ext_version_value (unsigned major, unsigned minor) +{ + return (major * 1000000) + (minor * 1000); +} + /* Implement TARGET_CPU_CPP_BUILTINS. */ void @@ -118,7 +124,11 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) builtin_define_with_int_value ("__riscv_v_elen_fp", 0); if (TARGET_MIN_VLEN) - builtin_define ("__riscv_vector"); + { + builtin_define ("__riscv_vector"); + builtin_define_with_int_value ("__riscv_v_intrinsic", + riscv_ext_version_value (0, 11)); + } /* Define architecture extension test macros. */ builtin_define_with_int_value ("__riscv_arch_test", 1); @@ -141,13 +151,13 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) subset != subset_list->end (); subset = subset->next) { - int version_value = (subset->major_version * 1000000) - + (subset->minor_version * 1000); + int version_value = riscv_ext_version_value (subset->major_version, + subset->minor_version); /* Special rule for zicsr and zifencei, it's used for ISA spec 2.2 or earlier. */ if ((subset->name == "zicsr" || subset->name == "zifencei") && version_value == 0) - version_value = 2000000; + version_value = riscv_ext_version_value (2, 0); sprintf (buf, "__riscv_%s", subset->name.c_str ()); builtin_define_with_int_value (buf, version_value); diff --git a/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c b/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c new file mode 100644 index 0000000..dbbedf5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64imafdcv -mabi=lp64d" } */ + +int main () { + +#if __riscv_v_intrinsic != 11000 +#error "__riscv_v_intrinsic" +#endif + + return 0; +} |