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| author | Michael Meissner <meissner@gcc.gnu.org> | 1994-06-15 02:44:18 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 1994-06-15 02:44:18 +0000 |
| commit | 4b71cd6ed2acc45f2b18dee38c5f91d7a5d5d90c (patch) | |
| tree | 95cbc2f145a6c5f24c429d554b47c0560520839a /gcc | |
| parent | 1ecba59dce5a2fa45bf77a8b2370536e313b5e1a (diff) | |
| download | gcc-4b71cd6ed2acc45f2b18dee38c5f91d7a5d5d90c.zip gcc-4b71cd6ed2acc45f2b18dee38c5f91d7a5d5d90c.tar.gz gcc-4b71cd6ed2acc45f2b18dee38c5f91d7a5d5d90c.tar.bz2 | |
Support 32x32->64 bit multiply
From-SVN: r7480
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/i386.h | 4 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 29 |
2 files changed, 28 insertions, 5 deletions
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index b69604b..7c60583 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -410,6 +410,7 @@ enum reg_class { NO_REGS, AREG, DREG, CREG, BREG, + AD_REGS, /* %eax/%edx for DImode */ Q_REGS, /* %eax %ebx %ecx %edx */ SIREG, DIREG, INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ @@ -428,6 +429,7 @@ enum reg_class #define REG_CLASS_NAMES \ { "NO_REGS", \ "AREG", "DREG", "CREG", "BREG", \ + "AD_REGS", \ "Q_REGS", \ "SIREG", "DIREG", \ "INDEX_REGS", \ @@ -443,6 +445,7 @@ enum reg_class #define REG_CLASS_CONTENTS \ { 0, \ 0x1, 0x2, 0x4, 0x8, /* AREG, DREG, CREG, BREG */ \ + 0x3, /* AD_REGS */ \ 0xf, /* Q_REGS */ \ 0x10, 0x20, /* SIREG, DIREG */ \ 0x1007f, /* INDEX_REGS */ \ @@ -514,6 +517,7 @@ extern enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; (C) == 'b' ? BREG : \ (C) == 'c' ? CREG : \ (C) == 'd' ? DREG : \ + (C) == 'A' ? AD_REGS : \ (C) == 'D' ? DIREG : \ (C) == 'S' ? SIREG : NO_REGS) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 9557032..3e43fb0 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -2343,15 +2343,34 @@ return AS3 (imul%L0,%2,%1,%0); }") -(define_insn "" +(define_insn "umulqihi3" [(set (match_operand:HI 0 "general_operand" "=a") - (mult:HI (zero_extend:HI - (match_operand:QI 1 "nonimmediate_operand" "%0")) - (zero_extend:HI - (match_operand:QI 2 "nonimmediate_operand" "qm"))))] + (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) + (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))] "" "mul%B0 %2") +(define_insn "mulqihi3" + [(set (match_operand:HI 0 "general_operand" "=a") + (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) + (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))] + "" + "imul%B0 %2") + +(define_insn "umulsidi3" + [(set (match_operand:DI 0 "register_operand" "=A") + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) + (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))] + "" + "mul%L0 %2") + +(define_insn "mulsidi3" + [(set (match_operand:DI 0 "register_operand" "=A") + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0")) + (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))] + "" + "imul%L0 %2") + ;; The patterns that match these are at the end of this file. (define_expand "mulxf3" |