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| author | John David Anglin <dave@hiauly1.hia.nrc.ca> | 2002-07-11 05:04:55 +0000 |
|---|---|---|
| committer | John David Anglin <danglin@gcc.gnu.org> | 2002-07-11 05:04:55 +0000 |
| commit | 47abc3093d32af09f50a6e49724322fa9885f374 (patch) | |
| tree | b6f327c73f19c4f23ef3a77bc75d6bb6d0b784a8 /gcc | |
| parent | 92ff302b2bbf33adfd6a37206e500d8202b28417 (diff) | |
| download | gcc-47abc3093d32af09f50a6e49724322fa9885f374.zip gcc-47abc3093d32af09f50a6e49724322fa9885f374.tar.gz gcc-47abc3093d32af09f50a6e49724322fa9885f374.tar.bz2 | |
pa.md (adddi3): For 32-bit targets...
* pa.md (adddi3): For 32-bit targets, force constants to a register
if they don't fit in an 11-bit immediate. Change insn predicate to
arith11_operand. Remove comment.
* pa.c (cint_ok_for_move): Fix comment.
(emit_move_sequence): Don't directly split DImode constants on 32-bit
targets.
From-SVN: r55389
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/pa/pa.c | 10 | ||||
| -rw-r--r-- | gcc/config/pa/pa.md | 18 |
3 files changed, 24 insertions, 13 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b94e96b..711a231 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2002-07-11 John David Anglin <dave@hiauly1.hia.nrc.ca> + + * pa.md (adddi3): For 32-bit targets, force constants to a register + if they don't fit in an 11-bit immediate. Change insn predicate to + arith11_operand. Remove comment. + * pa.c (cint_ok_for_move): Fix comment. + (emit_move_sequence): Don't directly split DImode constants on 32-bit + targets. + 2002-07-10 Roger Sayle <roger@eyesopen.com> PR c/2454 diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index 7661f59..c06a7b4 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -442,7 +442,7 @@ reg_before_reload_operand (op, mode) return 0; } -/* Accept any constant that can be moved in one instructions into a +/* Accept any constant that can be moved in one instruction into a general register. */ int cint_ok_for_move (intval) @@ -1744,9 +1744,13 @@ emit_move_sequence (operands, mode, scratch_reg) else temp = gen_reg_rtx (mode); - if (GET_CODE (operand1) == CONST_INT) + /* We don't directly split DImode constants on 32-bit targets + because PLUS uses an 11-bit immediate and the insn sequence + generated is not as efficient as the one using HIGH/LO_SUM. */ + if (GET_CODE (operand1) == CONST_INT + && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) { - /* Directly break constant into low and high parts. This + /* Directly break constant into high and low parts. This provides better optimization opportunities because various passes recognize constants split with PLUS but not LO_SUM. We use a 14-bit signed low part except when the addition diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index a814554..10c0462 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -3815,20 +3815,18 @@ (plus:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "arith_operand" "")))] "" - "") - -;; We allow arith_operand for operands2, even though strictly speaking it -;; we would prefer to us arith11_operand since that's what the hardware -;; can actually support. -;; -;; But the price of the extra reload in that case is worth the simplicity -;; we get by allowing a trivial adddi3 expander to be used for both -;; PA64 and PA32. + " +{ + if (!TARGET_64BIT + && GET_CODE (operands[2]) == CONST_INT + && !VAL_11_BITS_P (INTVAL (operands[2]))) + operands[2] = force_reg (DImode, operands[2]); +}") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (match_operand:DI 1 "register_operand" "%r") - (match_operand:DI 2 "arith_operand" "rI")))] + (match_operand:DI 2 "arith11_operand" "rI")))] "!TARGET_64BIT" "* { |