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| author | David Edelsohn <edelsohn@gnu.org> | 2005-08-13 18:47:08 +0000 |
|---|---|---|
| committer | David Edelsohn <dje@gcc.gnu.org> | 2005-08-13 14:47:08 -0400 |
| commit | 3256a76e621b4fd466ea9da5ce8de9a24a66aa0c (patch) | |
| tree | a8cf9cd6d7c86ffe2d57a6a6c7c45005101c77f4 /gcc | |
| parent | d77704579c02c48223abfe8db569941dfe0e4f46 (diff) | |
| download | gcc-3256a76e621b4fd466ea9da5ce8de9a24a66aa0c.zip gcc-3256a76e621b4fd466ea9da5ce8de9a24a66aa0c.tar.gz gcc-3256a76e621b4fd466ea9da5ce8de9a24a66aa0c.tar.bz2 | |
rs6000.h (EXTRA_CONSTRAINT): Add 'a' for indexed or indirect address operand.
* config/rs6000/rs6000.h (EXTRA_CONSTRAINT): Add 'a' for indexed
or indirect address operand.
(EXTRA_ADDRESS_CONSTRAINT): New.
* config/rs6000/rs6000.md (prefetch): Change constraint "p" to "a".
From-SVN: r103056
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.h | 8 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 2 |
3 files changed, 16 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4569677..1058d98 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2005-08-13 David Edelsohn <edelsohn@gnu.org> + + * config/rs6000/rs6000.h (EXTRA_CONSTRAINT): Add 'a' for indexed + or indirect address operand. + (EXTRA_ADDRESS_CONSTRAINT): New. + * config/rs6000/rs6000.md (prefetch): Change constraint "p" to "a". + 2005-08-13 Sebastian Pop <pop@cri.ensmp.fr> PR tree-optimization/22236 diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 17c98c0..bab54a9 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1111,6 +1111,7 @@ enum reg_class 'W' is a vector constant that can be easily generated (no mem refs). 'Y' is an indexed or word-aligned displacement memory operand. 'Z' is an indexed or indirect memory operand. + 'a' is an indexed or indirect address operand. 't' is for AND masks that can be performed by two rldic{l,r} insns. */ #define EXTRA_CONSTRAINT(OP, C) \ @@ -1127,6 +1128,7 @@ enum reg_class : (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP))) \ : (C) == 'Y' ? (word_offset_memref_operand (OP, GET_MODE (OP))) \ : (C) == 'Z' ? (indexed_or_indirect_operand (OP, GET_MODE (OP))) \ + : (C) == 'a' ? (indexed_or_indirect_address (OP, GET_MODE (OP))) \ : 0) /* Define which constraints are memory constraints. Tell reload @@ -1136,6 +1138,12 @@ enum reg_class #define EXTRA_MEMORY_CONSTRAINT(C, STR) \ ((C) == 'Q' || (C) == 'Y' || (C) == 'Z') +/* Define which constraints should be treated like address constraints + by the reload pass. */ + +#define EXTRA_ADDRESS_CONSTRAINT(C, STR) \ + ((C) == 'a') + /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 288b40f..c873c8f 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -14016,7 +14016,7 @@ }") (define_insn "prefetch" - [(prefetch (match_operand 0 "indexed_or_indirect_address" "p") + [(prefetch (match_operand 0 "indexed_or_indirect_address" "a") (match_operand:SI 1 "const_int_operand" "n") (match_operand:SI 2 "const_int_operand" "n"))] "TARGET_POWERPC" |