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| author | Kirill Yukhin <kirill.yukhin@intel.com> | 2016-04-15 08:25:49 +0000 |
|---|---|---|
| committer | Kirill Yukhin <kyukhin@gcc.gnu.org> | 2016-04-15 08:25:49 +0000 |
| commit | 1355e62cf8eb8a84fa706f1f2beefc56ea12be2d (patch) | |
| tree | 8bd08fbdcbcd7a2c21693a2dde67b15f6bf3cd2a /gcc | |
| parent | 0ab34b9e5a7dd2c56733c316859cb528ba3cfb84 (diff) | |
| download | gcc-1355e62cf8eb8a84fa706f1f2beefc56ea12be2d.zip gcc-1355e62cf8eb8a84fa706f1f2beefc56ea12be2d.tar.gz gcc-1355e62cf8eb8a84fa706f1f2beefc56ea12be2d.tar.bz2 | |
AVX-512. Fix mem operand modifier for Intel syntax.
PR target/70662
gcc/
* config/i386/sse.md: Use proper memory operand
modifiers.
testsuite/gcc/
* gcc.target/i386/pr70662.c: New test.
From-SVN: r235008
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 7 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr70662.c | 19 |
4 files changed, 36 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7d35837..8349e35 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2016-04-15 Kirill Yukhin <kirill.yukhin@intel.com> + + PR target/70662 + * config/i386/sse.md: Use proper memory operand + modifiers. + + 2016-04-15 Richard Biener <rguenther@suse.de> Alan Modra <amodra@gmail.com> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index b64457e..4d2927e 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -17262,9 +17262,12 @@ /* There is no DF broadcast (in AVX-512*) to 128b register. Mimic it with integer variant. */ if (<MODE>mode == V2DFmode) - return "vpbroadcastq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"; + return "vpbroadcastq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"; + + if (GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) == 32) + return "v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %k1}"; else - return "v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"; + return "v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"; } [(set_attr "type" "ssemov") (set_attr "prefix" "evex") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 69ea185..a62f7ec 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2016-04-15 Kirill Yukhin <kirill.yukhin@intel.com> + + PR target/70662 + * gcc.target/i386/pr70662.c: New test. + 2016-04-15 Richard Biener <rguenther@suse.de> Alan Modra <amodra@gmail.com> diff --git a/gcc/testsuite/gcc.target/i386/pr70662.c b/gcc/testsuite/gcc.target/i386/pr70662.c new file mode 100644 index 0000000..109e224 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr70662.c @@ -0,0 +1,19 @@ +/* { dg-do assemble { target { ! ia32 } } } */ +/* { dg-require-effective-target avx512vbmi } */ +/* { dg-require-effective-target masm_intel } */ +/* { dg-options "-Og -fschedule-insns -fno-tree-fre -mavx512vbmi --param=max-sched-ready-insns=1 -masm=intel" } */ + +typedef char v64u8 __attribute__((vector_size(64))); +typedef int v64u32 __attribute__((vector_size(64))); +typedef long v64u64 __attribute__((vector_size(64))); +typedef __int128 v64u128 __attribute__((vector_size(64))); + +v64u128 +foo(int u8_0, unsigned u128_0, v64u32 v64u32_1, v64u32 v64u32_0, v64u64 v64u64_0, v64u128 v64u128_0) +{ + v64u8 v64u8_0 = v64u8_0; + v64u32_0 = v64u32_0 >> (v64u32){0, 0, 0, 1, 0, ((v64u64)v64u64_0)[u8_0], ((v64u32)v64u128_0)[15], 0, 0, 0, 0, 4, ((v64u64)v64u64_0)[v64u32_0[0]] - 1}; + v64u8_0 = v64u8_0 << ((v64u8)v64u32_1 & 1); + v64u64_0[0] >>= 0; + return u128_0 + (v64u128)v64u8_0 + (v64u128)v64u32_0 + (v64u128)v64u64_0; +} |