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authorTakayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>2023-06-01 15:01:07 +0900
committerMax Filippov <jcmvbkbc@gmail.com>2023-06-01 07:13:45 -0700
commitfe3ce0861081dd17e581c32b299b9c743d000470 (patch)
treec5c2630e1d6e9beb482cd6896dfe7afc4c4c853f /gcc
parent3635e8c67e13e3da7e1e23a617dd9952218e93e0 (diff)
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xtensa: Add 'adddi3' and 'subdi3' insn patterns
More optimized than the default RTL generation. gcc/ChangeLog: * config/xtensa/xtensa.md (adddi3, subdi3): New RTL generation patterns implemented according to the instruc- tion idioms described in the Xtensa ISA reference manual (p. 600).
Diffstat (limited to 'gcc')
-rw-r--r--gcc/config/xtensa/xtensa.md52
1 files changed, 52 insertions, 0 deletions
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index eda1353..21afa74 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -190,6 +190,35 @@
(set_attr "mode" "SI")
(set_attr "length" "3")])
+(define_expand "adddi3"
+ [(set (match_operand:DI 0 "register_operand")
+ (plus:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "register_operand")))]
+ ""
+{
+ rtx lo_dest, hi_dest, lo_op0, hi_op0, lo_op1, hi_op1;
+ rtx_code_label *label;
+ if (rtx_equal_p (operands[0], operands[1])
+ || rtx_equal_p (operands[0], operands[2])
+ || ! REG_P (operands[1]) || ! REG_P (operands[2]))
+ FAIL;
+ lo_dest = gen_lowpart (SImode, operands[0]);
+ hi_dest = gen_highpart (SImode, operands[0]);
+ lo_op0 = gen_lowpart (SImode, operands[1]);
+ hi_op0 = gen_highpart (SImode, operands[1]);
+ lo_op1 = gen_lowpart (SImode, operands[2]);
+ hi_op1 = gen_highpart (SImode, operands[2]);
+ emit_insn (gen_addsi3 (hi_dest, hi_op0, hi_op1));
+ emit_insn (gen_addsi3 (lo_dest, lo_op0, lo_op1));
+ emit_cmp_and_jump_insns (lo_dest,
+ (REGNO (operands[1]) < REGNO (operands[2])
+ ? lo_op1 : lo_op0), GEU, const0_rtx,
+ SImode, true, label = gen_label_rtx ());
+ emit_insn (gen_addsi3 (hi_dest, hi_dest, const1_rtx));
+ emit_label (label);
+ DONE;
+})
+
(define_insn "addsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
(plus:SF (match_operand:SF 1 "register_operand" "%f")
@@ -237,6 +266,29 @@
(const_int 5)
(const_int 6)))])
+(define_expand "subdi3"
+ [(set (match_operand:DI 0 "register_operand")
+ (minus:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "register_operand")))]
+ ""
+{
+ rtx lo_dest, hi_dest, lo_op0, hi_op0, lo_op1, hi_op1;
+ rtx_code_label *label;
+ lo_dest = gen_lowpart (SImode, operands[0]);
+ hi_dest = gen_highpart (SImode, operands[0]);
+ lo_op0 = gen_lowpart (SImode, operands[1]);
+ hi_op0 = gen_highpart (SImode, operands[1]);
+ lo_op1 = gen_lowpart (SImode, operands[2]);
+ hi_op1 = gen_highpart (SImode, operands[2]);
+ emit_insn (gen_subsi3 (hi_dest, hi_op0, hi_op1));
+ emit_cmp_and_jump_insns (lo_op0, lo_op1, GEU, const0_rtx,
+ SImode, true, label = gen_label_rtx ());
+ emit_insn (gen_addsi3 (hi_dest, hi_dest, constm1_rtx));
+ emit_label (label);
+ emit_insn (gen_subsi3 (lo_dest, lo_op0, lo_op1));
+ DONE;
+})
+
(define_insn "subsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
(minus:SF (match_operand:SF 1 "register_operand" "f")