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| author | Alex Coplan <alex.coplan@arm.com> | 2023-05-25 13:34:46 +0100 |
|---|---|---|
| committer | Alex Coplan <alex.coplan@arm.com> | 2023-05-25 13:34:46 +0100 |
| commit | f5298d9969b4fa34ff3aecd54b9630e22b2984a5 (patch) | |
| tree | c30d07103845dfa1c391e5f1d892e9a956b63207 /gcc | |
| parent | f97572c2aeddc71b01686993b978895e55890ab6 (diff) | |
| download | gcc-f5298d9969b4fa34ff3aecd54b9630e22b2984a5.zip gcc-f5298d9969b4fa34ff3aecd54b9630e22b2984a5.tar.gz gcc-f5298d9969b4fa34ff3aecd54b9630e22b2984a5.tar.bz2 | |
arm: Fix ICE due to infinite splitting [PR109800]
In r11-966-g9a182ef9ee011935d827ab5c6c9a7cd8e22257d8 we introduce a
simplification to emit_move_insn that attempts to simplify moves of the form:
(set (subreg:M1 (reg:M2 ...)) (constant C))
where M1 and M2 are of equal mode size. That is problematic for the splitter
vfp.md:no_literal_pool_df_immediate in the arm backend, which tries to pun an
lvalue DFmode pseudo into DImode and assign a constant to it with
emit_move_insn, as the new transformation simply undoes this, and we end up
splitting indefinitely.
This patch changes things around in the arm backend so that we use a
DImode temporary (instead of DFmode) and first load the DImode constant
into the pseudo, and then pun the pseudo into DFmode as an rvalue in a
reg -> reg move. I believe this should be semantically equivalent but
avoids the pathalogical behaviour seen in the PR.
gcc/ChangeLog:
PR target/109800
* config/arm/arm.md (movdf): Generate temporary pseudo in DImode
instead of DFmode.
* config/arm/vfp.md (no_literal_pool_df_immediate): Rather than punning an
lvalue DFmode pseudo into DImode, use a DImode pseudo and pun it into
DFmode as an rvalue.
gcc/testsuite/ChangeLog:
PR target/109800
* gcc.target/arm/pure-code/pr109800.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/arm/arm.md | 2 | ||||
| -rw-r--r-- | gcc/config/arm/vfp.md | 7 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/pure-code/pr109800.c | 4 |
3 files changed, 9 insertions, 4 deletions
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index cbfc454..40c4d84 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -7555,7 +7555,7 @@ && !arm_const_double_rtx (operands[1]) && !(TARGET_VFP_DOUBLE && vfp3_const_double_rtx (operands[1]))) { - rtx clobreg = gen_reg_rtx (DFmode); + rtx clobreg = gen_reg_rtx (DImode); emit_insn (gen_no_literal_pool_df_immediate (operands[0], operands[1], clobreg)); DONE; diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 60e7ba3..03514ac 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -2138,7 +2138,7 @@ (define_insn_and_split "no_literal_pool_df_immediate" [(set (match_operand:DF 0 "s_register_operand" "=w") (match_operand:DF 1 "const_double_operand" "F")) - (clobber (match_operand:DF 2 "s_register_operand" "=r"))] + (clobber (match_operand:DI 2 "s_register_operand" "=r"))] "arm_disable_literal_pool && TARGET_VFP_BASE && !arm_const_double_rtx (operands[1]) @@ -2153,8 +2153,9 @@ unsigned HOST_WIDE_INT ival = zext_hwi (buf[order], 32); ival |= (zext_hwi (buf[1 - order], 32) << 32); rtx cst = gen_int_mode (ival, DImode); - emit_move_insn (simplify_gen_subreg (DImode, operands[2], DFmode, 0), cst); - emit_move_insn (operands[0], operands[2]); + emit_move_insn (operands[2], cst); + emit_move_insn (operands[0], + simplify_gen_subreg (DFmode, operands[2], DImode, 0)); DONE; } ) diff --git a/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c b/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c new file mode 100644 index 0000000..d797b79 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pure-code/pr109800.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_hard_ok } */ +/* { dg-options "-O2 -march=armv7-m -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mbig-endian -mpure-code" } */ +double f() { return 5.0; } |