RISC-V: Support RVV VFMSAC rounding mode intrinsic API

This patch would like to support the rounding mode API for the
VFMSAC for the below samples.

* __riscv_vfmsac_vv_f32m1_rm
* __riscv_vfmsac_vv_f32m1_rm_m
* __riscv_vfmsac_vf_f32m1_rm
* __riscv_vfmsac_vf_f32m1_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(class vfmsac_frm): New class for vfmsac frm.
	(vfmsac_frm_obj): New declaration.
	(BASE): Ditto.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def
	(vfmsac_frm): New function definition

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-msac.c: New test.

4 files changed, 75 insertions, 0 deletions

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 1d4a5a1..8d3970b 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -401,6 +401,29 @@ public:
   }
 };
 
+/* Implements below instructions for frm
+   - vfmsac
+*/
+class vfmsac_frm : public function_base
+{
+public:
+  bool has_rounding_mode_operand_p () const override { return true; }
+
+  bool has_merge_operand_p () const override { return false; }
+
+  rtx expand (function_expander &e) const override
+  {
+    if (e.op_info->op == OP_TYPE_vf)
+      return e.use_ternop_insn (
+	true, code_for_pred_mul_scalar (MINUS, e.vector_mode ()));
+    if (e.op_info->op == OP_TYPE_vv)
+      return e.use_ternop_insn (
+	true, code_for_pred_mul (MINUS, e.vector_mode ()));
+
+    gcc_unreachable ();
+  }
+};
+
 /* Implements vrsub.  */
 class vrsub : public function_base
 {
@@ -2168,6 +2191,7 @@ static CONSTEXPR const vfnmsub vfnmsub_obj;
 static CONSTEXPR const vfnmacc vfnmacc_obj;
 static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj;
 static CONSTEXPR const vfmsac vfmsac_obj;
+static CONSTEXPR const vfmsac_frm vfmsac_frm_obj;
 static CONSTEXPR const vfnmadd vfnmadd_obj;
 static CONSTEXPR const vfmsub vfmsub_obj;
 static CONSTEXPR const vfwmacc vfwmacc_obj;
@@ -2405,6 +2429,7 @@ BASE (vfnmsub)
 BASE (vfnmacc)
 BASE (vfnmacc_frm)
 BASE (vfmsac)
+BASE (vfmsac_frm)
 BASE (vfnmadd)
 BASE (vfmsub)
 BASE (vfwmacc)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 247074d..ca8a6dc 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -167,6 +167,7 @@ extern const function_base *const vfnmsub;
 extern const function_base *const vfnmacc;
 extern const function_base *const vfnmacc_frm;
 extern const function_base *const vfmsac;
+extern const function_base *const vfmsac_frm;
 extern const function_base *const vfnmadd;
 extern const function_base *const vfmsub;
 extern const function_base *const vfwmacc;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 7aae066..51a14e4 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -353,6 +353,8 @@ DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvvv_ops)
 DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvfv_ops)
 DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvvv_ops)
 DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvfv_ops)
+DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f_vvvv_ops)
+DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f_vvfv_ops)
 
 // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
 DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msac.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msac.c
new file mode 100644
index 0000000..8fee552
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msac.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfmsac_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
+			       vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfmsac_vv_f32m1_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfmsac_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+			   vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfmsac_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
+test_vfmsac_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2,
+			 size_t vl) {
+  return __riscv_vfmsac_vf_f32m1_rm (vd, op1, op2, 2, vl);
+}
+
+vfloat32m1_t
+test_vfmsac_vf_f32m1_rm_m (vfloat32m1_t vd, vbool32_t mask, float32_t op1,
+			   vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfmsac_vf_f32m1_rm_m (mask, vd, op1, op2, 3, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfmsac_vv_f32m1 (vfloat32m1_t vd, vfloat32m1_t op1,
+			    vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfmsac_vv_f32m1 (vd, op1, op2, vl);
+}
+
+vfloat32m1_t
+test_vfmsac_vv_f32m1_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+			vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfmsac_vv_f32m1_m (mask, vd, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfmsac\.v[vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*v[0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */