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| author | Richard Sandiford <richard.sandiford@arm.com> | 2015-07-05 07:51:07 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2015-07-05 07:51:07 +0000 |
| commit | eb6f47fb90994bc9021b42119a51f56aa706fe14 (patch) | |
| tree | d03fee8436802cd55820f4aa8cc8096a090c3417 /gcc | |
| parent | 134b044daf0999cee9f85203be3fa35c48051da1 (diff) | |
| download | gcc-eb6f47fb90994bc9021b42119a51f56aa706fe14.zip gcc-eb6f47fb90994bc9021b42119a51f56aa706fe14.tar.gz gcc-eb6f47fb90994bc9021b42119a51f56aa706fe14.tar.bz2 | |
target-insns.def (trap): New targetm instruction pattern.
gcc/
* target-insns.def (trap): New targetm instruction pattern.
* builtins.c (expand_builtin_trap): Use it instead of HAVE_*/gen_*
interface.
* explow.c (allocate_dynamic_stack_space): Likewise.
* ifcvt.c (find_if_header): Likewise.
From-SVN: r225425
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/builtins.c | 6 | ||||
| -rw-r--r-- | gcc/explow.c | 6 | ||||
| -rw-r--r-- | gcc/ifcvt.c | 5 | ||||
| -rw-r--r-- | gcc/target-insns.def | 1 |
5 files changed, 14 insertions, 12 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2129526..848d4db 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,13 @@ 2015-07-05 Richard Sandiford <richard.sandiford@arm.com> + * target-insns.def (trap): New targetm instruction pattern. + * builtins.c (expand_builtin_trap): Use it instead of HAVE_*/gen_* + interface. + * explow.c (allocate_dynamic_stack_space): Likewise. + * ifcvt.c (find_if_header): Likewise. + +2015-07-05 Richard Sandiford <richard.sandiford@arm.com> + * target-insns.def (prefetch): New targetm instruction pattern. * tree-ssa-loop-prefetch.c: Include targeth. (tree_ssa_prefetch_arrays): Use prefetch targetm pattern instead diff --git a/gcc/builtins.c b/gcc/builtins.c index b98bb06..d953c63 100644 --- a/gcc/builtins.c +++ b/gcc/builtins.c @@ -4737,10 +4737,9 @@ expand_builtin_assume_aligned (tree exp, rtx target) void expand_builtin_trap (void) { -#ifdef HAVE_trap - if (HAVE_trap) + if (targetm.have_trap ()) { - rtx_insn *insn = emit_insn (gen_trap ()); + rtx_insn *insn = emit_insn (targetm.gen_trap ()); /* For trap insns when not accumulating outgoing args force REG_ARGS_SIZE note to prevent crossjumping of calls with different args sizes. */ @@ -4748,7 +4747,6 @@ expand_builtin_trap (void) add_reg_note (insn, REG_ARGS_SIZE, GEN_INT (stack_pointer_delta)); } else -#endif emit_library_call (abort_libfunc, LCT_NORETURN, VOIDmode, 0); emit_barrier (); } diff --git a/gcc/explow.c b/gcc/explow.c index adc17a3..c2158f3 100644 --- a/gcc/explow.c +++ b/gcc/explow.c @@ -1422,11 +1422,9 @@ allocate_dynamic_stack_space (rtx size, unsigned size_align, emit_cmp_and_jump_insns (available, size, GEU, NULL_RTX, Pmode, 1, space_available); -#ifdef HAVE_trap - if (HAVE_trap) - emit_insn (gen_trap ()); + if (targetm.have_trap ()) + emit_insn (targetm.gen_trap ()); else -#endif error ("stack limits not supported on this target"); emit_barrier (); emit_label (space_available); diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c index 6e20557..f796799 100644 --- a/gcc/ifcvt.c +++ b/gcc/ifcvt.c @@ -67,9 +67,6 @@ #ifndef HAVE_decscc #define HAVE_decscc 0 #endif -#ifndef HAVE_trap -#define HAVE_trap 0 -#endif #ifndef MAX_CONDITIONAL_EXECUTE #define MAX_CONDITIONAL_EXECUTE \ @@ -3414,7 +3411,7 @@ find_if_header (basic_block test_bb, int pass) && cond_exec_find_if_block (&ce_info)) goto success; - if (HAVE_trap + if (targetm.have_trap () && optab_handler (ctrap_optab, word_mode) != CODE_FOR_nothing && find_cond_trap (test_bb, then_edge, else_edge)) goto success; diff --git a/gcc/target-insns.def b/gcc/target-insns.def index 45a7008..33e112e 100644 --- a/gcc/target-insns.def +++ b/gcc/target-insns.def @@ -51,5 +51,6 @@ DEF_TARGET_INSN (sibcall_epilogue, (void)) DEF_TARGET_INSN (simple_return, (void)) DEF_TARGET_INSN (store_multiple, (rtx x0, rtx x1, rtx x2)) DEF_TARGET_INSN (tablejump, (rtx x0, rtx x1)) +DEF_TARGET_INSN (trap, (void)) DEF_TARGET_INSN (untyped_call, (rtx x0, rtx x1, rtx x2)) DEF_TARGET_INSN (untyped_return, (rtx x0, rtx x1)) |