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| author | Xi Ruoyao <xry111@xry111.site> | 2023-12-19 05:02:42 +0800 |
|---|---|---|
| committer | Xi Ruoyao <xry111@xry111.site> | 2023-12-20 20:01:51 +0800 |
| commit | e61c51009145bab05cdc00e06a7dbc4209cb580e (patch) | |
| tree | 2f7bc95e4c36ae053518d68f9d34495de0d5456e /gcc | |
| parent | c7eefea622e70bd63b0e00e896f67cf9ee9916bc (diff) | |
| download | gcc-e61c51009145bab05cdc00e06a7dbc4209cb580e.zip gcc-e61c51009145bab05cdc00e06a7dbc4209cb580e.tar.gz gcc-e61c51009145bab05cdc00e06a7dbc4209cb580e.tar.bz2 | |
LoongArch: Clean up vec_init expander
Non functional change, clean up the code.
gcc/ChangeLog:
* config/loongarch/loongarch.cc
(loongarch_expand_vector_init_same): Remove "temp2" and reuse
"temp" instead.
(loongarch_expand_vector_init): Use gcc_unreachable () instead
of gcc_assert (0), and fix the comment for it.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/loongarch/loongarch.cc | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index cb5a831..a5b1dad 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -10728,7 +10728,7 @@ loongarch_expand_vector_init_same (rtx target, rtx vals, unsigned nvar) machine_mode vmode = GET_MODE (target); machine_mode imode = GET_MODE_INNER (vmode); rtx same = XVECEXP (vals, 0, 0); - rtx temp, temp2; + rtx temp; if (CONST_INT_P (same) && nvar == 0 && loongarch_signed_immediate_p (INTVAL (same), 10, 0)) @@ -10752,17 +10752,17 @@ loongarch_expand_vector_init_same (rtx target, rtx vals, unsigned nvar) } if (imode == GET_MODE (same)) - temp2 = same; + temp = same; else if (GET_MODE_SIZE (imode) >= UNITS_PER_WORD) { if (GET_CODE (same) == MEM) { rtx reg_tmp = gen_reg_rtx (GET_MODE (same)); loongarch_emit_move (reg_tmp, same); - temp2 = simplify_gen_subreg (imode, reg_tmp, GET_MODE (reg_tmp), 0); + temp = simplify_gen_subreg (imode, reg_tmp, GET_MODE (reg_tmp), 0); } else - temp2 = simplify_gen_subreg (imode, same, GET_MODE (same), 0); + temp = simplify_gen_subreg (imode, same, GET_MODE (same), 0); } else { @@ -10770,13 +10770,13 @@ loongarch_expand_vector_init_same (rtx target, rtx vals, unsigned nvar) { rtx reg_tmp = gen_reg_rtx (GET_MODE (same)); loongarch_emit_move (reg_tmp, same); - temp2 = lowpart_subreg (imode, reg_tmp, GET_MODE (reg_tmp)); + temp = lowpart_subreg (imode, reg_tmp, GET_MODE (reg_tmp)); } else - temp2 = lowpart_subreg (imode, same, GET_MODE (same)); + temp = lowpart_subreg (imode, same, GET_MODE (same)); } - temp = force_reg (imode, temp2); + temp = force_reg (imode, temp); switch (vmode) { @@ -11122,8 +11122,8 @@ loongarch_expand_vector_init (rtx target, rtx vals) return; } - /* Loongson is the only cpu with vectors with more elements. */ - gcc_assert (0); + /* No LoongArch CPU supports vectors with more elements as at now. */ + gcc_unreachable (); } /* Implement HARD_REGNO_CALLER_SAVE_MODE. */ |