diff options
| author | Saurabh Jha <saurabh.jha@arm.com> | 2023-11-14 14:48:40 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2023-11-14 14:49:46 +0000 |
| commit | ddb479e796bee3964ddb6a2daa8f79598e47cede (patch) | |
| tree | fa8c370ad3d5716719f523d3e8e4899dba221d6b /gcc | |
| parent | 2066c29bf8dea87c9810eb261e342d941a6b2059 (diff) | |
| download | gcc-ddb479e796bee3964ddb6a2daa8f79598e47cede.zip gcc-ddb479e796bee3964ddb6a2daa8f79598e47cede.tar.gz gcc-ddb479e796bee3964ddb6a2daa8f79598e47cede.tar.bz2 | |
Add a REG_P check for inc and dec for Arm MVE
This patch tightens mve_vector_mem_operand to reject non-register operands inside {PRE,POST}_{INC,DEC} addresses by introducing a REG_P check.
This patch fixes this ICE:https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112337
gcc/ChangeLog:
PR target/112337
* config/arm/arm.cc (mve_vector_mem_operand): Add a REG_P check for INC
and DEC operations.
gcc/testsuite/ChangeLog:
PR target/112337
* gcc.target/arm/mve/pr112337.c: Test for REG_P check for INC and DEC
operations.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/arm/arm.cc | 7 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/mve/pr112337.c | 15 |
2 files changed, 20 insertions, 2 deletions
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 620ef7b..25a1ad7 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -13695,8 +13695,11 @@ mve_vector_mem_operand (machine_mode mode, rtx op, bool strict) } code = GET_CODE (op); - if (code == POST_INC || code == PRE_DEC - || code == PRE_INC || code == POST_DEC) + if ((code == POST_INC + || code == PRE_DEC + || code == PRE_INC + || code == POST_DEC) + && REG_P (XEXP (op, 0))) { reg_no = arm_effective_regno (XEXP (op, 0), strict); return (((mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode) diff --git a/gcc/testsuite/gcc.target/arm/mve/pr112337.c b/gcc/testsuite/gcc.target/arm/mve/pr112337.c new file mode 100644 index 0000000..8f49199 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/pr112337.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +#include <arm_mve.h> + +void g(int32x4_t); +void f(int, int, int, short, int *p) { + int *bias = p; + for (;;) { + int32x4_t d = vldrwq_s32 (p); + bias += 4; + g(d); + } +} |