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| author | Wilco Dijkstra <wdijkstr@arm.com> | 2015-07-27 15:02:55 +0000 |
|---|---|---|
| committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2015-07-27 15:02:55 +0000 |
| commit | d99dacc9484b29b9223526264bc055905c31b08c (patch) | |
| tree | e094bd2f12ea6a2fedaaa8362c0885538ca47a59 /gcc | |
| parent | 02bcdc56ee26b35137c2c5be74915c6461c9b4cc (diff) | |
| download | gcc-d99dacc9484b29b9223526264bc055905c31b08c.zip gcc-d99dacc9484b29b9223526264bc055905c31b08c.tar.gz gcc-d99dacc9484b29b9223526264bc055905c31b08c.tar.bz2 | |
[PATCH][AArch64] Improve spill code - swap order in shl pattern
gcc/
* config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_<mode>3):
Place integer variant first.
From-SVN: r226247
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 14 |
2 files changed, 12 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0a9ae7f..00b9b99 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2015-07-27 Wilco Dijkstra <wdijkstr@arm.com> + + * config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_<mode>3): + Place integer variant first. + 2015-07-27 Matthew Wahab <matthew.wahab@arm.com> * config/arm/arm-arches.def: Add "armv6kz". Replace 6ZK with 6KZ diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index f264534..65e4c66 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3523,17 +3523,17 @@ ;; Logical left shift using SISD or Integer instruction (define_insn "*aarch64_ashl_sisd_or_int_<mode>3" - [(set (match_operand:GPI 0 "register_operand" "=w,w,r") + [(set (match_operand:GPI 0 "register_operand" "=r,w,w") (ashift:GPI - (match_operand:GPI 1 "register_operand" "w,w,r") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "Us<cmode>,w,rUs<cmode>")))] + (match_operand:GPI 1 "register_operand" "r,w,w") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "rUs<cmode>,Us<cmode>,w")))] "" "@ + lsl\t%<w>0, %<w>1, %<w>2 shl\t%<rtn>0<vas>, %<rtn>1<vas>, %2 - ushl\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas> - lsl\t%<w>0, %<w>1, %<w>2" - [(set_attr "simd" "yes,yes,no") - (set_attr "type" "neon_shift_imm<q>, neon_shift_reg<q>,shift_reg")] + ushl\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas>" + [(set_attr "simd" "no,yes,yes") + (set_attr "type" "shift_reg,neon_shift_imm<q>, neon_shift_reg<q>")] ) ;; Logical right shift using SISD or Integer instruction |